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Taha Soliman
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2020 – today
- 2024
- [c16]Yannick Braatz, Taha Soliman, Shubham Rai
, Dennis Sebastian Rieber, Oliver Bringmann:
CoNAX: Towards Comprehensive Co-Design Neural Architecture Search Using HW Abstractions. ASAP 2024: 8-16 - [c15]Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn:
Error Detection and Correction Codes for Safe In-Memory Computations. ETS 2024: 1-4 - [c14]Joseph Rogers, Taha Soliman, Magnus Jahre:
AIO: An Abstraction for Performance Analysis Across Diverse Accelerator Architectures. ISCA 2024: 487-500 - [c13]Shubham Rai, Cecilia De la Parra, Martin Rapp, Jan Micha Borrmann, Nina Bretz, Stefan Metzlaff, Taha Soliman, Christoph Schorn:
Accelerating Automated Driving and ADAS Using HW/SW Codesign. SOCC 2024: 1-6 - [i1]Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn:
Error Detection and Correction Codes for Safe In-Memory Computations. CoRR abs/2404.09818 (2024) - 2023
- [j4]Vivek Parmar
Demonstration of Differential Mode Ferroelectric Field-Effect Transistor Array-Based in-Memory Computing Macro for Realizing Multiprecision Mixed-Signal Artificial Intelligence Accelerator. Adv. Intell. Syst. 5(6) (2023) - [c12]Yannick Braatz, Dennis Sebastian Rieber, Taha Soliman, Oliver Bringmann:
Simulation-driven Latency Estimations for Multi-core Machine Learning Accelerators. AICAS 2023: 1-5 - [c11]Yannick Braatz, Dennis Sebastian Rieber, Taha Soliman, Oliver Bringmann:
SimPyler: A Compiler-Based Simulation Framework for Machine Learning Accelerators. ASAP 2023: 213-220 - [c10]Nellie Laleni, Taha Soliman, Cecilia De la Parra, Franz Müller, Tobias Kirchner, Andre Guntoro, Thomas Kämpfe, Norbert Wehn, T. Jang:
Torwards Variability Immune Scalable FeFET-based Macros for IMC DNN Accelerators. ICECS 2023: 1-4 - 2022
- [b1]Taha Soliman:
Ultra-low power approximate processing-in-memory acceleration for deep neural networks = Approximative Prozessierung viellagiger neuronaler Netze in Speichermatrizen für Systeme mit ultra-geringer Leistungsaufnahme. Kaiserslautern University of Technology, Germany, 2022, ISBN 978-3-95974-197-2, pp. 1-168 - [j3]Chirag Sudarshan
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 367-380 (2022) - [j2]Cecilia De la Parra
Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation. IEEE Micro 42(6): 17-24 (2022) - [j1]Taha Soliman
FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration. ACM Trans. Embed. Comput. Syst. 21(6): 84:1-84:25 (2022) - [c9]Taha Soliman, Amro Eldebiky, Cecilia De la Parra, Andre Guntoro, Norbert Wehn:
Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators. SOCC 2022: 1-6 - [c8]Chirag Sudarshan, Taha Soliman, Thomas Kämpfe
FeFET versus DRAM based PIM Architectures: A Comparative Study. VLSI-SoC 2022: 1-6 - 2021
- [c7]Taha Soliman, Cecilia De la Parra, Andre Guntoro
Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators. AICAS 2021: 1-4 - [c6]Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung, Norbert Wehn, Andre Guntoro
A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. ASP-DAC 2021: 35-42 - [c5]Cecilia De la Parra, Ahmed El-Yamany, Taha Soliman, Akash Kumar
Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design. ISCAS 2021: 1-5 - 2020
- [c4]Taha Soliman, Ricardo Olivo, Tobias Kirchner, Cecilia De la Parra, Maximilian Lederer
Efficient FeFET Crossbar Accelerator for Binary Neural Networks. ASAP 2020: 109-112 - [c3]Taha Soliman, Armin Runge, Leonardo Ecco:
Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators. IPDPS Workshops 2020: 840-843 - [c2]Taha Soliman, Ricardo Olivo, Tobias Kirchner, Maximilian Lederer
A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks. SoCC 2020: 96-101
2010 – 2019
- 2019
- [c1]Matthias Jung, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn
Fast validation of DRAM protocols with timed petri nets. MEMSYS 2019: 133-147
Coauthor Index
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