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Sylvain Barraud
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2020 – today
- 2024
- [c20]Ancelin Salerno, Sylvain Barraud:
Evaluation and implementation of High-Dimensionnal Computing for gesture recognition using sEMG signals. ICCAD 2024: 1-6 - 2023
- [c19]T. Dubreuil, Sylvain Barraud, J.-M. Pedini, Jean-Michel Hartmann, F. Boulard, A. Sarrazin, A. Gharbi, Johannes Sturm, A. Lambert, S. Martin, Niccolo Castellani, A. Anotta, A. Magalhaes-Lucas, Aurelie Souhaite, François Andrieu:
Integration of HfO2-based 3D OxRAM with GAA stacked-nanosheet transistor for high-density embedded memory. ESSDERC 2023: 117-120 - 2022
- [c18]T. Dubreuil, P. Amari, Sylvain Barraud, Joris Lacord, Eduardo Esmanhotto, Valentina Meli, S. Martin, Niccolo Castellani, Bernard Previtali, François Andrieu:
A novel 3D 1T1R RRAM architecture for memory-centric Hyperdimensional Computing. IMW 2022: 1-4 - 2021
- [c17]R. Midahuen, Bernard Previtali, C. Fontelaye, G. Nonglaton, Sylvain Barraud, V. Stambouli:
Wafer-scale fabrication of biologically sensitive Si nanowire FET: from pH sensing to electrical detection of DNA hybridization. ESSCIRC 2021: 175-178 - [c16]R. Midahuen, Bernard Previtali, C. Fontelaye, G. Nonglaton, V. Stambouli, Sylvain Barraud:
Wafer-scale fabrication of biologically sensitive Si nanowire FET: from pH sensing to electrical detection of DNA hybridization. ESSDERC 2021: 175-178 - [c15]Michelly de Souza
, Sylvain Barraud, Mikaël Cassé, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello:
Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors. ESSDERC 2021: 223-226 - 2020
- [i1]Mona Ezzadeen, D. Bosch, Bastien Giraud, Sylvain Barraud, Jean-Philippe Noël, Didier Lattard, Joris Lacord, Jean-Michel Portal, François Andrieu:
Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. CoRR abs/2012.00061 (2020)
2010 – 2019
- 2019
- [c14]Renan Trevisoli
Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors. ESSDERC 2019: 194-197 - 2018
- [c13]Maud Vinet, Louis Hutin, Benoit Bertrand, Heorhii Bohuslavskyi, Andrea Corna, Anthony Amisse, Alessandro Crippa
Towards scalable silicon quantum computing. DRC 2018: 1-2 - [c12]Louis Hutin, Benoit Bertrand, Romain Maurand, Alessandro Crippa
Si MOS technology for spin-based quantum computing. ESSDERC 2018: 12-17 - [c11]Antoine Laurent, Xavier Garros, Sylvain Barraud, J. Pelloux-Prayer
Performance & reliability of 3D architectures (πfet, Finfet, Ωfet). IRPS 2018: 6 - 2017
- [j3]Bruna Cardoso Paz, Renan Trevisoli Doria, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello:
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K. Microelectron. Reliab. 79: 111-118 (2017) - [c10]Renan Trevisoli Doria
A new method for junctionless transistors parameters extraction. ESSDERC 2017: 66-69 - [c9]Louis Hutin, Benoit Bertrand, Romain Maurand, Matias Urdampilleta
SOI CMOS technology for quantum information processing. ICICDT 2017: 1-4 - 2016
- [j2]Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Olivier Faynot, F. Avila-Herrera, Antonio Cerdeira, Marcelo Antonio Pavanello:
Drain current model for short-channel triple gate junctionless nanowire transistors. Microelectron. Reliab. 63: 1-10 (2016) - [c8]R. Lavieville, Theano A. Karatsori, Christoforos G. Theodorou
Statistical characterization of drain current local and global variability in sub 15nm Si/SiGe Trigate pMOSFETs. ESSDERC 2016: 142-145 - [c7]Bruna Cardoso Paz, Marcelo Antonio Pavanello, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot:
Analog performance of strained SOI nanowires down to 10K. ESSDERC 2016: 222-225 - 2015
- [c6]J. Pelloux-Prayer
Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model. ESSDERC 2015: 210-213 - [c5]Mukta Singh Parihar
Back-gate effects and detailed characterization of junctionless transistor. ESSDERC 2015: 282-285 - 2013
- [c4]Remi Coquand, Sylvain Barraud, Mikaël Cassé, Masahiro Koyama, Virginie Maffini-Alvaro, Marie-Pierre Samson, Lucie Tosti, Xavier Mescot, Gérard Ghibaudo, Stéphane Monfray, Frédéric Boeuf, Olivier Faynot, Barbara De Salvo:
Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations. ESSDERC 2013: 198-201 - [c3]Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Gérard Ghibaudo
Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs. ESSDERC 2013: 300-303 - 2012
- [c2]Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Hiroshi Iwai, Gérard Ghibaudo, Gilles Reimbold:
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs. ESSDERC 2012: 73-76 - [c1]Veeresh Deshpande, Sylvain Barraud, Xavier Jehl, Romain Wacquez, Maud Vinet, Remi Coquand, B. Roche, B. Voisin, François Triozon
Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities. ESSDERC 2012: 121-124 - 2011
- [j1]Kiichi Tachi, Sylvain Barraud, Kuniyuki Kakushima, Hiroshi Iwai, Sorin Cristoloveanu, Thomas Ernst
Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs. Microelectron. Reliab. 51(5): 885-888 (2011)
Coauthor Index
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last updated on 2024-10-07 22:18 CEST by the dblp team
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