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Vijay Nagarajan
Person information
- affiliation: University of Utah, Salt Lake City, UT, USA
- affiliation: University of Edinburgh
- affiliation (Ph.D., 2009): University of California, Riverside, CA, USA
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2020 – today
- 2024
- [c57]An Qi Zhang
, Andrés Goens
PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model. PACT 2024: 1-13 - [c56]Weihang Li, Andrés Goens, Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin:
Determining the Minimum Number of Virtual Networks for Different Coherence Protocols. ISCA 2024: 182-197 - 2023
- [j15]Nicolai Oswald
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. IEEE Micro 43(4): 62-70 (2023) - [j14]Andrés Goens
Compound Memory Models. Proc. ACM Program. Lang. 7(PLDI): 1145-1168 (2023) - [c55]Adarsh Patil, Vijay Nagarajan, Nikos Nikoleris, Nicolai Oswald:
Āpta: Fault-tolerant object-granular CXL disaggregated memory for accelerating FaaS. DSN 2023: 201-215 - 2022
- [c54]Nicolai Oswald, Vijay Nagarajan
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. HPCA 2022: 756-771 - 2021
- [c53]Vasilis Gavrielatos, Vijay Nagarajan, Panagiota Fatourou:
Towards the Synthesis of Coherence/Replication Protocols from Consistency Models via Real-Time Orderings. PaPoC@EuroSys 2021: 5:1-5:10 - [c52]Vasilis Gavrielatos, Antonios Katsarakis, Vijay Nagarajan
Odyssey: the impact of modern hardware on strongly-consistent replication protocols. EuroSys 2021: 245-260 - [c51]Adarsh Patil
Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication. ISCA 2021: 526-539 - [c50]Maurice Bailleu, Dimitra Giantsidi, Vasilis Gavrielatos, Do Le Quoc, Vijay Nagarajan, Pramod Bhatotia:
Avocado: A Secure In-Memory Distributed Storage System. USENIX ATC 2021: 65-79 - [i3]Vasilis Gavrielatos, Antonios Katsarakis, Vijay Nagarajan:
Extending Classic Paxos for High-performance Read-Modify-Write Registers. CoRR abs/2103.14701 (2021) - 2020
- [b2]Vijay Nagarajan
A Primer on Memory Consistency and Cache Coherence, Second Edition. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2020, ISBN 978-3-031-00636-4 - [c49]Antonios Katsarakis, Vasilis Gavrielatos, M. R. Siavash Katebzadeh, Arpit Joshi, Aleksandar Dragojevic, Boris Grot
Hermes: A Fast, Fault-Tolerant and Linearizable Replication Protocol. ASPLOS 2020: 201-217 - [c48]Mahesh Dananjaya, Vasilis Gavrielatos, Arpit Joshi, Vijay Nagarajan
Lazy Release Persistency. ASPLOS 2020: 1173-1186 - [c47]Nicolai Oswald, Vijay Nagarajan
HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols. ISCA 2020: 888-899 - [c46]Vasilis Gavrielatos, Antonios Katsarakis, Vijay Nagarajan
Kite: efficient and available release consistency for the datacenter. PPoPP 2020: 1-16 - [i2]Antonios Katsarakis, Vasilis Gavrielatos, M. R. Siavash Katebzadeh, Arpit Joshi, Aleksandar Dragojevic, Boris Grot, Vijay Nagarajan:
Hermes: a Fast, Fault-Tolerant and Linearizable Replication Protocol. CoRR abs/2001.09804 (2020)
2010 – 2019
- 2019
- [c45]Saumay Dublish, Vijay Nagarajan, Nigel P. Topham:
Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs Using Machine Learning. HPCA 2019: 492-505 - 2018
- [j13]José Cano
Solving the task variant allocation problem in distributed robotics. Auton. Robots 42(7): 1477-1495 (2018) - [c44]Rakesh Kumar, Boris Grot
Blasting through the Front-End Bottleneck with Shotgun. ASPLOS 2018: 30-42 - [c43]Marco Elver, Christopher J. Banks
VerC3: A library for explicit state synthesis of concurrent systems. DATE 2018: 1381-1386 - [c42]Vasilis Gavrielatos, Antonios Katsarakis, Arpit Joshi, Nicolai Oswald, Boris Grot
Scale-out ccNUMA: exploiting skew with strongly consistent caching. EuroSys 2018: 21:1-21:15 - [c41]José Cano
Automatic Parameter Tuning of Motion Planning Algorithms. IROS 2018: 8103-8109 - [c40]Nicolai Oswald, Vijay Nagarajan
ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications. ISCA 2018: 247-260 - [c39]Arpit Joshi, Vijay Nagarajan
DHTM: Durable Hardware Transactional Memory. ISCA 2018: 452-465 - 2017
- [c38]Christopher J. Banks
Verification of a lazy cache coherence protocol against a weak memory model. FMCAD 2017: 60-67 - [c37]Arpit Joshi, Vijay Nagarajan
ATOM: Atomic Durability in Non-volatile Memory through Hardware Logging. HPCA 2017: 361-372 - [c36]Rakesh Kumar, Cheng-Chieh Huang, Boris Grot
Boomerang: A Metadata-Free Architecture for Control Flow Delivery. HPCA 2017: 493-504 - [c35]Saumay Dublish, Vijay Nagarajan, Nigel P. Topham:
Evaluating and mitigating bandwidth bottlenecks across the memory hierarchy in GPUs. ISPASS 2017: 239-248 - [e1]Vijay Nagarajan, Zili Shao:
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2017, Barcelona, Spain, June 21-22, 2017. ACM 2017, ISBN 978-1-4503-5030-3 [contents] - [i1]Christopher J. Banks, Marco Elver, Ruth Hoffmann, Susmit Sarkar, Paul B. Jackson, Vijay Nagarajan:
Verification of a lazy cache coherence protocol against a weak memory model. CoRR abs/1705.08262 (2017) - 2016
- [j12]Andrew J. McPherson, Vijay Nagarajan, Susmit Sarkar
Fence Placement for Legacy Data-Race-Free Programs via Synchronization Read Detection. ACM Trans. Archit. Code Optim. 12(4): 46:1-46:23 (2016) - [j11]Saumay Dublish, Vijay Nagarajan, Nigel P. Topham:
Cooperative Caching for GPUs. ACM Trans. Archit. Code Optim. 13(4): 39:1-39:25 (2016) - [c34]Marco Elver, Vijay Nagarajan:
McVerSi: A test generation framework for fast memory consistency verification in simulation. HPCA 2016: 618-630 - [c33]Saumay Dublish, Vijay Nagarajan, Nigel P. Topham:
Characterizing memory bottlenecks in GPGPU workloads. IISWC 2016: 229-230 - [c32]José Cano
Automatic configuration of ROS applications for near-optimal performance. IROS 2016: 2217-2223 - [c31]Cheng-Chieh Huang, Rakesh Kumar, Marco Elver, Boris Grot
C3D: Mitigating the NUMA bottleneck via coherent DRAM caches. MICRO 2016: 36:1-36:12 - [c30]José Cano
Task Variant Allocation in Distributed Robotics. Robotics: Science and Systems 2016 - [c29]Cheng-Chieh Huang, Vijay Nagarajan, Arpit Joshi:
DCA: a DRAM-cache-aware DRAM controller. SC 2016: 887-897 - 2015
- [c28]Marco Elver, Vijay Nagarajan:
RC3: Consistency Directed Cache Coherence for x86-64 with RC Extensions. PACT 2015: 292-304 - [c27]José Cano
Dynamic process migration in heterogeneous ROS-based environments. ICAR 2015: 518-523 - [c26]Arpit Joshi, Vijay Nagarajan, Marcelo Cintra, Stratis Viglas:
Efficient persist barriers for multicores. MICRO 2015: 660-671 - [c25]Andrew J. McPherson, Vijay Nagarajan, Susmit Sarkar
Fence placement for legacy data-race-free programs via synchronization read detection. PPoPP 2015: 249-250 - [c24]Georgios Stefanakis, Vijay Nagarajan, Marcelo Cintra:
Understanding the Effects of Data Corruption on Application Behavior Based on Data Characteristics. SAFECOMP 2015: 151-165 - 2014
- [j10]Vijay Nagarajan, Dennis Jeffrey, Rajiv Gupta
Erratum: A system for debugging via online tracing and dynamic slicing. Softw. Pract. Exp. 44(9): 1155 (2014) - [c23]Cheng-Chieh Huang, Vijay Nagarajan:
ATCache: reducing DRAM cache latency via a small SRAM tag cache. PACT 2014: 51-60 - [c22]Marco Elver, Vijay Nagarajan:
TSO-CC: Consistency directed cache coherence for TSO. HPCA 2014: 165-176 - [c21]Cheng-Chieh Huang, Vijay Nagarajan:
Increasing cache capacity via critical-words-only cache. ICCD 2014: 125-132 - [c20]Andrew J. McPherson, Vijay Nagarajan, Marcelo Cintra:
Static Approximation of MPI Communication Graphs for Optimized Process Placement. LCPC 2014: 268-283 - [c19]Changhui Lin, Vijay Nagarajan, Rajiv Gupta
Fence Scoping. SC 2014: 105-116 - 2013
- [c18]Changhui Lin, Vijay Nagarajan, Rajiv Gupta
Address-aware fences. ICS 2013: 313-324 - [c17]Bharghava Rajaram, Vijay Nagarajan, Susmit Sarkar
Fast RMWs for TSO: semantics and implementation. PLDI 2013: 61-72 - 2012
- [j9]Changhui Lin, Vijay Nagarajan, Rajiv Gupta
Efficient Sequential Consistency Using Conditional Fences. Int. J. Parallel Program. 40(1): 84-117 (2012) - [j8]Vijay Nagarajan, Dennis Jeffrey, Rajiv Gupta
A system for debugging via online tracing and dynamic slicing. Softw. Pract. Exp. 42(8): 995-1014 (2012) - [j7]Vijay Nagarajan, Dennis Jeffrey, Rajiv Gupta
Erratum: A system for debugging via online tracing and dynamic slicing. Softw. Pract. Exp. 42(11): 1431 (2012) - [c16]Changhui Lin, Vijay Nagarajan, Rajiv Gupta
Efficient sequential consistency via conflict ordering. ASPLOS 2012: 273-286 - [c15]Bharghava Rajaram, Vijay Nagarajan, Andrew J. McPherson, Marcelo Cintra:
SuperCoP: a general, correct, and performance-efficient supervised memory system. Conf. Computing Frontiers 2012: 85-94 - 2010
- [j6]Dennis Jeffrey, Vijay Nagarajan, Rajiv Gupta
Execution suppression: An automated iterative technique for locating memory errors. ACM Trans. Program. Lang. Syst. 32(5): 17:1-17:36 (2010) - [c14]Changhui Lin, Vijay Nagarajan, Rajiv Gupta
Efficient sequential consistency using conditional fences. PACT 2010: 295-306
2000 – 2009
- 2009
- [b1]Vijayanand Nagarajan:
IMPRESS: Improving Multicore Performance and Reliability via Efficient Software Support for Monitoring. University of California, Riverside, USA, 2009 - [j5]Chen Tian, Min Feng, Vijay Nagarajan, Rajiv Gupta
Speculative Parallelization of Sequential Loops on Multicores. Int. J. Parallel Program. 37(5): 508-535 (2009) - [j4]Vijay Nagarajan, Rajiv Gupta
Runtime monitoring on multicores via OASES. ACM SIGOPS Oper. Syst. Rev. 43(2): 15-24 (2009) - [j3]Chen Tian, Vijay Nagarajan, Rajiv Gupta
Automated dynamic detection of busy-wait synchronizations. Softw. Pract. Exp. 39(11): 947-972 (2009) - [j2]Vijay Nagarajan, Rajiv Gupta
Compiler-Assisted Memory Encryption for Embedded Processors. Trans. High Perform. Embed. Archit. Compil. 2: 23-44 (2009) - [c13]Vijay Nagarajan, Rajiv Gupta
ECMon: exposing cache events for monitoring. ISCA 2009: 349-360 - [c12]Vijay Nagarajan, Dennis Jeffrey, Rajiv Gupta
Self-recovery in server programs. ISMM 2009: 49-58 - [c11]Vijay Nagarajan, Rajiv Gupta
Speculative Optimizations for Parallel Programs on Multicores. LCPC 2009: 323-337 - [c10]Vijay Nagarajan, Rajiv Gupta
Architectural support for shadow memory in multiprocessors. VEE 2009: 1-10 - 2008
- [c9]Rajiv Gupta
Scalable dynamic information flow tracking and its applications. IPDPS 2008: 1-5 - [c8]Vijay Nagarajan, Rajiv Gupta:
Support for symmetric shadow memory in multiprocessors. PADTAD 2008: 5 - [c7]Chen Tian, Vijay Nagarajan, Rajiv Gupta
Dynamic recognition of synchronization operations for improved data race detection. ISSTA 2008: 143-154 - [c6]Chen Tian, Min Feng, Vijay Nagarajan, Rajiv Gupta
Copy or Discard execution model for speculative parallelization on multicores. MICRO 2008: 330-341 - 2007
- [j1]Vijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri:
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. J. VLSI Signal Process. 49(1): 185-206 (2007) - [c5]Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy:
Compiler-Assisted Memory Encryption for Embedded Processors. HiPEAC 2007: 7-22 - [c4]Vijayanand Nagarajan, Rajiv Gupta
Matching Control Flow of Program Versions. ICSM 2007: 84-93 - [c3]Vijayanand Nagarajan, Dennis Jeffrey, Rajiv Gupta
ONTRAC: A system for efficient ONline TRACing for debugging. ICSM 2007: 445-454 - 2004
- [c2]Vijay Nagarajan, Nikhil Jayakumar, Sunil P. Khatri, Olgica Milenkovic:
High-throughput VLSI implementations of iterative decoders and related code construction problems. GLOBECOM 2004: 361-365 - [c1]Vijay Nagarajan, Youjian Liu
The effect of channel side information at transmitter on coding complexity. ISIT 2004: 148
Coauthor Index
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