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Masakazu Yamashina
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2000 – 2009
- 2002
- [j16]Masakazu Yamashina, Shekhar Y. Borkar:
Guest editorial. IEEE J. Solid State Circuits 37(5): 535 (2002) - [c5]Hiroyuki Igura, Masaru Hirata, Junya Yamada, Masakazu Yamashina, Shigeru Ono:
A low-power W-CDMA demodulator using specially-designed micro-DSPs. CICC 2002: 397-400 - 2001
- [j15]David B. Scott, Masakazu Yamashina:
Guest editorial. IEEE J. Solid State Circuits 36(5): 724-725 (2001) - 2000
- [j14]Masato Edahiro, Satoshi Matsushita, Masakazu Yamashina, Naoki Nishi:
A Single-Chip Multiprocessor for Smart Terminals. IEEE Micro 20(4): 12-20 (2000) - [c4]Masakazu Yamashina, Masato Motomura
:
Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk. ASP-DAC 2000: 329-332 - [c3]Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina:
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. CICC 2000: 151-154
1990 – 1999
- 1999
- [j13]Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina:
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. IEEE J. Solid State Circuits 34(7): 1010-1021 (1999) - 1998
- [j12]Hiroyuki Igura, Yukihiro Naito, Kenya Kazama, Ichiro Kuroda, Masato Motomura
An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing. IEEE J. Solid State Circuits 33(11): 1820-1828 (1998) - [c2]Masato Motomura
An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. FCCM 1998: 264-266 - 1997
- [j11]Masanori Izumikawa, Hiroyuki Igura, Hitoshi Wakabayashi, Ken Nakajima, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina:
A 0.25-μm CMOS 0.9-V 100-MHz DSP core. IEEE J. Solid State Circuits 32(1): 52-61 (1997) - [j10]Masayuki Mizuno, Yasushi Ooi, Naoya Hayashi, Junichi Goto, Masatoshi Hozumi, Koichiro Furuta, Atsufumi Shibayama, Yoetsu Nakazawa, Osamu Ohnishi, Shu-Yu Zhu, Yutaka Yokoyama, Yoichi Katayama, Hideto Takano, Noriyuki Miki, Yuzo Senda, Ichiro Tamitani, Masakazu Yamashina:
A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. IEEE J. Solid State Circuits 32(11): 1807-1816 (1997) - [c1]Yasushi Ooi, Osamu Ohnishi, Yutaka Yokoyama, Yoichi Katayama, Masayuki Mizuno, Masakazu Yamashina, Hideo Takano, Naoya Hayashi, Ichiro Tamitani:
An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU. ICASSP 1997: 599-602 - 1996
- [j9]Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina:
Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. IEEE J. Solid State Circuits 31(4): 531-536 (1996) - [j8]Masanori Izumikawa, Masakazu Yamashina:
A current direction sense technique for multiport SRAM's. IEEE J. Solid State Circuits 31(4): 546-551 (1996) - [j7]Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada:
A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE J. Solid State Circuits 31(6): 784-791 (1996) - 1995
- [j6]Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina:
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. IEEE J. Solid State Circuits 30(6): 637-643 (1995) - 1994
- [j5]Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. IEEE J. Solid State Circuits 29(3): 290-297 (1994) - [j4]Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina:
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. IEEE J. Solid State Circuits 29(11): 1336-1343 (1994) - [j3]Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada:
A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. IEEE J. Solid State Circuits 29(12): 1464-1473 (1994)
1980 – 1989
- 1989
- [j2]Masakazu Yamashina, Junichi Goto, Fuyuki Okamoto, Koichi Ando, Hachiro Yamada, Tadahiko Horiuchi, Kimiko Nakamura, Tadayoshi Enomoto:
A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI. IEEE J. Solid State Circuits 24(6): 1668-1674 (1989) - 1988
- [j1]Masakazu Yamashina, Tadayoshi Enomoto, Takemitsu Kunio, Ichiro Tamitani, Hidenobu Harasaki, Yukio Endo, Takao Nishitani, Masao Satoh, Koichi Kikuchi:
A microprogrammable real-time video signal processor (VSP) for motion compensation. IEEE J. Solid State Circuits 23(4): 907-915 (1988)
Coauthor Index
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