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Salvatore N. Storino
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2010 – 2019
- 2011
- [c3]Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter F. Wendel, Leland Chang:
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. ISSCC 2011: 256-258
2000 – 2009
- 2005
- [c2]Tom Beacom, Timothy C. Buchholtz, D. Bradley, Jack Randolph, Salvatore N. Storino, Mark Veldhuizen, Sherman M. Dance, Jente B. Kuang, Steve Schwinn, Sue Cox, Fred Ziegler, J. Kao, Chuck Li, Christophe Tretz, J. Cabellon, Andrew Freemyer, Matthew Tubbs:
Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor. CICC 2005: 235-238 - 2001
- [j2]Daniel L. Stasiak, Farnaz Mounes-Toussi, Salvatore N. Storino:
A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology. IEEE J. Solid State Circuits 36(10): 1546-1552 (2001)
1990 – 1999
- 1999
- [j1]Anthony G. Aipperspach, David H. Allen, Dennis T. Cox, Nghia Phan, Salvatore N. Storino:
A 0.2-μm, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects. IEEE J. Solid State Circuits 34(11): 1430-1435 (1999) - [c1]J. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak:
SOI Implementation of a 64-Bit Adder. ICCD 1999: 573-
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