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Jinwu Chen
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2020 – today
- 2024
- [j3]Jinwu Chen
, Yitong Zhao
An INT8 Charge-Digital Hybrid Compute-In-Memory Macro With CNN-Friendly Shift-Feed Register Design. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1371-1375 (2024) - [j2]Xi Chen, Yitong Zhao
Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 3181-3185 (2024) - [c5]Zhaoyang Zhang, Zhichao Liu, Feiran Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Xingyu Pu, Xing Wang, Jun Yang, Xin Si:
A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. CICC 2024: 1-2 - [c4]An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si:
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. ISSCC 2024: 570-572 - 2023
- [j1]Zhaoyang Zhang, Jinwu Chen, Xi Chen, An Guo, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xingyu Pu, Shengnan He, Xin Si, Jun Yang:
From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. Sci. China Inf. Sci. 66(10) (2023) - [c3]Yiran Zhang, Bo Wang, Jinwu Chen, Xi Chen, Xin Si:
Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits. MCSoC 2023: 160-165 - 2022
- [c2]Jinwu Chen, Tianzhu Xiong, Xin Si:
A Charge-Digital Hybrid Compute-In-Memory Macro with full precision 8-bit Multiply-Accumulation for Edge Computing Devices. MCSoC 2022: 153-158
2010 – 2019
- 2011
- [c1]Erkang Cheng, Jinwu Chen, Jie Yang, Huiyang Deng
Automatic Dent-landmark detection in 3-D CBCT dental volumes. EMBC 2011: 6204-6207
Coauthor Index
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