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Milan Radulovic
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2020 – today
- 2021
- [c10]Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir
, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero
Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS 2021: 18-29
2010 – 2019
- 2019
- [b1]Milan Radulovic:
Memory bandwidth and latency in HPC: system requirements and performance impact. Polytechnic University of Catalonia, Spain, 2019 - [j2]Milan Radulovic, Rommel Sánchez Verdejo, Paul M. Carpenter, Petar Radojkovic, Bruce L. Jacob, Eduard Ayguadé:
PROFET: Modeling System Performance and Energy Without Simulating the CPU. Proc. ACM Meas. Anal. Comput. Syst. 3(2): 34:1-34:33 (2019) - [c9]Milan Radulovic
PROFET: Modeling System Performance and Energy Without Simulating the CPU. SIGMETRICS (Abstracts) 2019: 71-72 - 2018
- [c8]Milan Radulovic
HPC Benchmarking: Scaling Right and Looking Beyond the Average. Euro-Par 2018: 135-146 - [c7]Rommel Sánchez Verdejo, Kazi Asifuzzaman
Main memory latency simulation: the missing link. MEMSYS 2018: 107-116 - [c6]Milan Radulovic
Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned. SBAC-PAD 2018: 250-257 - 2017
- [j1]Darko Zivanovic
Main Memory in HPC: Do We Need More or Could We Live with Less? ACM Trans. Archit. Code Optim. 14(1): 3:1-3:26 (2017) - 2016
- [c5]Darko Zivanovic
Large-Memory Nodes for Energy Efficient High-Performance Computing. MEMSYS 2016: 3-9 - [c4]Kazi Asifuzzaman
Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC. MEMSYS 2016: 40-49 - 2015
- [c3]Milan Pavlovic, Milan Radulovic, Alex Ramírez, Petar Radojkovic:
Limpio: LIghtweight MPI instrumentatiOn. ICPC 2015: 303-306 - [c2]Milan Radulovic
Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC? MEMSYS 2015: 31-36 - 2013
- [c1]Milan Radulovic
Industrial Single Board Computer based on OMAP5 processor. MECO 2013: 84-87
Coauthor Index
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