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Walter M. Weber
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2020 – today
- 2024
- [c14]Daniele Nazzari, Lukas Wind, Dominik Mayr, Kihye Kim, Sebastian Lellig, Masiar Sistani, Walter M. Weber:
Realization and characterization of HZO-based Schottky-Barrier FETs towards Logic-in-Memory applications. DRC 2024: 1-3 - [c13]Lukas Wind, A. Fuchsberger, Masiar Sistani, Walter M. Weber
:
Three-Input Combinational Logic Gates based on Reconfigurable Si Field-Effect Transistors. DRC 2024: 1-2 - [i1]Daniele Nazzari, Lukas Wind, Masiar Sistani, Dominik Mayr, Kihye Kim, Walter M. Weber:
Ferroelectrically-enhanced Schottky barrier transistors for Logic-in-Memory applications. CoRR abs/2404.19535 (2024) - 2023
- [c12]Raphael Behrle, Martien I. Den Hertog, Alois Lugstein, Walter M. Weber, Masiar Sistani:
Bias Spectroscopy of Negative Differential Resistance in Ge Nanowire Cascode Circuits. ESSDERC 2023: 37-40 - 2022
- [c11]Christian Römer, Ghader Darbandy, Mike Schwarz, Jens Trommer
Compact Modeling of Channel-Resistance Effects in Reconfigurable Field-Effect Transistors. MIXDES 2022: 33-39
2010 – 2019
- 2019
- [j1]Shubham Rai
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 560-572 (2019) - [c10]Sabine Kolodinski, Boli Peng, Ciro Esposito, Yves Zimmermann, Michael Schröter, Xin Xu, Paolo Valerio Testa, Corrado Carta
IPCEI subcontracts contributing to 22-FDX Add-On Functionalities at GF. ESSDERC 2019: 74-77 - [c9]Jens Trommer
Eliminating Charge Sharing in Clocked Logic Gates on the Device Level Employing Transistors with Multiple Independent Inputs. ESSDERC 2019: 134-137 - 2018
- [c8]Shubham Rai
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs. DATE 2018: 605-608 - [c7]Maik Simon
A wired-AND transistor: Polarity controllable FET with multiple inputs. DRC 2018: 1-2 - 2017
- [c6]Michael Raitza, Akash Kumar, Marcus Völp
Exploiting transistor-level reconfiguration to optimize combinational circuits. DATE 2017: 338-343 - [c5]Dae-Young Jeon, Tim Baldauf, So Jeong Park, Sebastian Pregl, Larysa Baraban
In-depth electrical characterization of carrier transport in ambipolar Si-NW Schottky-barrier FETs. ESSDERC 2017: 304-307 - [c4]Lotta Romhildt, Felix Zorgiebel, Bergoi Ibarlucea
Human α-thrombin detection platform using aptamers on a silicon nanowire field-effect transistor. PATMOS 2017: 1-4 - 2016
- [c3]Jens Trommer, Andre Heinzig, Tim Baldauf, Thomas Mikolajick, Walter M. Weber, Michael Raitza, Marcus Völp
Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits. DATE 2016: 169-174 - 2014
- [c2]Walter M. Weber, Jens Trommer
Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges. DATE 2014: 1-6 - 2013
- [c1]Walter M. Weber, Jens Trommer
Reconfigurable nanowire electronics - Device principles and circuit prospects. ESSDERC 2013: 246-251
Coauthor Index
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