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Henrique Cota de Freitas
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- affiliation: Pontifícia Universidade Católica de Minas Gerais, Belo Horizonte, Brazil
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2020 – today
- 2024
- [j18]Matheus Alcântara Souza
, Henrique C. Freitas
Reinforcement Learning-Based Cache Replacement Policies for Multicore Processors. IEEE Access 12: 79177-79188 (2024) - [j17]Lucas Andrade Maciel
Energy-Efficient CPU+FPGA-Based CNN Architecture for Intrusion Detection Systems. IEEE Consumer Electron. Mag. 13(4): 65-72 (2024) - [j16]Felipe Augusto Lara Soares
Automated and intelligent system for World Health Organization data forecasting. Expert Syst. J. Knowl. Eng. 41(4) (2024) - 2023
- [j15]João Fellipe Uller, João Vicente Souto, Pedro Henrique Penna, Márcio Castro
LWMPI: An MPI library for NoC-based lightweight manycore processors with on-chip memory constraints. Concurr. Comput. Pract. Exp. 35(17) (2023) - [c27]André Alves, Luis E. Zárate, Henrique C. Freitas
Parallelism in the Generation of Concepts Through the Formal Context Object Partitioning Using the In-Close 4 Algorithm. ICEIS (2) 2023: 195-202 - 2021
- [j14]João P. P. Novais
An open computing language-based parallel Brute Force algorithm for formal concept analysis on heterogeneous architectures. Concurr. Comput. Pract. Exp. 33(18) (2021) - [j13]Pedro Henrique Penna
Co-Designing Clusters of Lightweight Manycores and Asymmetric Operating System Kernels. IEEE Embed. Syst. Lett. 13(4): 178-181 (2021) - [j12]Pedro Henrique Penna
Inter-kernel communication facility of a distributed operating system for NoC-based lightweight manycores. J. Parallel Distributed Comput. 154: 1-15 (2021) - 2020
- [j11]Lucas Andrade Maciel
Reconfigurable FPGA-Based K-Means/K-Modes Architecture for Network Intrusion Detection. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1459-1463 (2020) - [c26]Tiago Batista da Silveira
Fast and Efficient Parallel Execution of SARIMA Prediction Model. ICEIS (Revised Selected Papers) 2020: 217-241 - [c25]Felipe A. L. Soares, Tiago B. Silveira, Henrique C. Freitas
Hybrid Approach based on SARIMA and Artificial Neural Networks for Knowledge Discovery Applied to Crime Rates Prediction. ICEIS (1) 2020: 407-415
2010 – 2019
- 2019
- [j10]Pedro Henrique Penna
A comprehensive performance evaluation of the BinLPT workload-aware loop scheduler. Concurr. Comput. Pract. Exp. 31(18) (2019) - [j9]Guilherme Torres Castro, Luis Enrique Zárate
A Fast Parallel K-Modes Algorithm for Clustering Nucleotide Sequences to Predict Translation Initiation Sites. J. Comput. Biol. 26(5): 442-456 (2019) - [c24]Leonardo B. A. Vasconcelos, Felipe A. L. Soares, Pedro Henrique de Mello Morado Penna, Max V. Machado, Luís Fabrício Wanderley Góes
Teaching Parallel Programming to Freshmen in an Undergraduate Computer Science Program. FIE 2019: 1-8 - [c23]Pedro Henrique Penna
On the Performance and Isolation of Asymmetric Microkernel Design for Lightweight Manycores. SBESC 2019: 1-8 - 2018
- [c22]Matheus Alcântara Souza, Lucas Andrade Maciel
Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package. SBAC-PAD 2018: 372-379 - [c21]Matheus Alcântara Souza, Henrique C. Freitas
Design Space Exploration of Energy Efficient NoC-and Cache-Based Many-Core Architecture. SBAC-PAD 2018: 402-409 - 2017
- [j8]Matheus Alcântara Souza, Pedro Henrique Penna
CAP Bench: a benchmark suite for performance and energy evaluation of low-power many-core processors. Concurr. Comput. Pract. Exp. 29(4) (2017) - [j7]Pedro Henrique Penna
Design methodology for workload-aware loop scheduling strategies based on genetic algorithm and simulation. Concurr. Comput. Pract. Exp. 29(22) (2017) - [j6]Cássio Alves Carneiro, Francisco M. P. Garcia, Henrique C. Freitas
Scalable spatio-temporal parallel parameterizable stream-based JPEG-LS encoder. IEICE Electron. Express 14(2): 20160950 (2017) - [c20]Pedro Henrique Penna
Assessing the Performance of the SRR Loop Scheduler with Irregular Workloads. ICCS 2017: 255-264 - [c19]Matheus Alcântara Souza, Tulio T. Cota, Matheus M. Queiroz, Henrique C. Freitas
Energy Consumption Improvement of Shared-Cache Multicore Clusters Based on Explicit Simultaneous Multithreading. SBAC-PAD (Workshops) 2017: 1-6 - [c18]Pedro Henrique de Mello Morado Penna
Using the Nanvix Operating System in Undergraduate Operating System Courses. SBESC 2017: 193-198 - 2016
- [j5]Nilander R. M. de Moraes, Sérgio M. Dias, Henrique C. Freitas, Luis E. Zárate:
Parallelization of the next Closure algorithm for generating the minimum set of implication rules. Artif. Intell. Res. 5(2): 40-54 (2016) - [c17]João Saffran, Gabriel Garcia, Matheus Alcântara Souza, Pedro Henrique Penna
A Low-Cost Energy-Efficient Raspberry Pi Cluster for Data Mining Algorithms. Euro-Par Workshops 2016: 788-799 - 2015
- [j4]Amanda M. P. Amorim, Poliana A. C. Oliveira, Henrique C. Freitas
Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks. J. Braz. Comput. Soc. 21(1): 6 (2015) - [j3]Emilio Francesquini
On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms. J. Parallel Distributed Comput. 76: 32-48 (2015) - 2013
- [c16]Henrique Cota de Freitas
Method for teaching parallelism on heterogeneous many-core processors using research projects. FIE 2013: 108-113 - 2012
- [c15]Henrique Cota de Freitas
Introducing parallel programming to traditional undergraduate courses. FIE 2012: 1-6 - [c14]Laerte M. Rodrigues, Luis E. Zárate
Parallel and distributed kmeans to identify the translation initiation site of proteins. SMC 2012: 1639-1645 - 2011
- [j2]Mateus B. Rutzig
Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment. Int. J. Reconfigurable Comput. 2011: 546962:1-546962:13 (2011) - [j1]Marco A. Z. Alves
High Latency and Contention on Shared L2-Cache for Many-Core Architectures. Parallel Process. Lett. 21(1): 85-106 (2011) - 2010
- [c13]Nilander R. M. de Moraes, Luis E. Zárate, Henrique C. Freitas:
A Distributed Algorithm for Formal Concepts Processing based on Search Subspaces. ICEIS (1) 2010: 105-111 - [c12]Mateus B. Rutzig
TLP and ILP exploitation through a reconfigurable multiprocessor system. IPDPS Workshops 2010: 1-8 - [c11]Felipe Lopes Madruga, Henrique Cota de Freitas
Parallel Shared-Memory Workloads Performance on Asymmetric Multi-core Architectures. PDP 2010: 163-169 - [c10]Henrique Cota de Freitas
Impact of Parallel Workloads on NoC Architecture Design. PDP 2010: 551-555
2000 – 2009
- 2009
- [b1]Henrique Cota de Freitas:
Programmable multi-cluster noc architecture to support collective communication patterns. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil, 2009 - [c9]Henrique Cota de Freitas
On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers. ACM Great Lakes Symposium on VLSI 2009: 129-132 - [c8]Henrique C. Freitas
Design of Interleaved Multithreading for Network Processors on Chip. ISCAS 2009: 2213-2216 - [c7]Henrique C. Freitas
Performance Evaluation of NoC Architectures for Parallel Workloads. NOCS 2009: 87 - 2008
- [c6]Henrique C. Freitas
A High-Throughput Multi-cluster NoC Architecture. CSE 2008: 56-63 - [c5]Henrique C. Freitas
NOC architecture design for multi-cluster chips. FPL 2008: 53-58 - 2007
- [c4]Henrique C. Freitas
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs. ISCAS 2007: 3776-3779 - 2006
- [c3]Henrique C. Freitas
Reconfigurable crossbar switch architecture for network processors. ISCAS 2006 - 2003
- [c2]Henrique Cota de Freitas
Didactic architectures and simulator for network processor learning. WCAE 2003: 14 - 2001
- [c1]Jorge Luis Nicolas Audy, João Luiz Becker, Henrique C. Freitas:
Information Systems Planning: Contributions from Organizational Learning. ICEIS (2) 2001: 873-879
Coauthor Index
aka: Márcio Bastos Castro
aka: Philippe O. A. Navaux
aka: Pedro Henrique Penna
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