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Takashi Hirayama
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2020 – today
- 2024
- [j11]Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani:
New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. IEICE Trans. Inf. Syst. 107(8): 940-948 (2024) - [c10]Takashi Hirayama, Ryo Endo, Katsuhisa Yamanaka:
An Improved Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. ISMVL 2024: 120-125 - 2023
- [j10]Shunta Terui, Katsuhisa Yamanaka, Takashi Hirayama, Takashi Horiyama, Kazuhiro Kurita, Takeaki Uno:
Enumerating Empty and Surrounding Polygons. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(9): 1082-1091 (2023) - [c9]Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani:
Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. ISMVL 2023: 153-157 - 2022
- [j9]Taishu Ito, Yusuke Sano, Katsuhisa Yamanaka, Takashi Hirayama:
A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs. IEICE Trans. Inf. Syst. 105-D(3): 466-473 (2022) - 2020
- [c8]Yusuke Sano, Katsuhisa Yamanaka, Takashi Hirayama:
A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs. FAW 2020: 13-24
2010 – 2019
- 2019
- [j8]Katsuhisa Yamanaka, Shogo Kawaragi, Takashi Hirayama:
Exact Exponential Algorithm for Distance-3 Independent Set Problem. IEICE Trans. Inf. Syst. 102-D(3): 499-501 (2019) - 2018
- [j7]Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani:
Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2231-2243 (2018) - 2016
- [c7]Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani:
New Two-Qubit Gate Library with Entanglement. ISMVL 2016: 235-240 - 2014
- [j6]Takashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani:
A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. IEICE Trans. Inf. Syst. 97-D(9): 2253-2261 (2014) - 2011
- [c6]Takashi Hirayama, Yasuaki Nishitani, Seiji Kitamura:
A Testable Realization for Decimal Multipliers. ISMVL 2011: 248-253
2000 – 2009
- 2009
- [j5]Takashi Hirayama, Yasuaki Nishitani:
Exact Minimization of and-EXOR Expressions of Practical Benchmark Functions. J. Circuits Syst. Comput. 18(3): 465-486 (2009) - [c5]Takashi Hirayama:
Let's make a tennis game!: introduction to game programming. SIGGRAPH ASIA Courses 2009 - 2006
- [c4]Takashi Hirayama, Masatoshi Takahashi, Yasuaki Nishitani:
Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation. APCCAS 2006: 1480-1483 - [c3]Takashi Hirayama, Yasuaki Nishitani:
Efficient Search Methods for Obtaining Exact Minimum AND-EXOR Expressions. DELTA 2006: 137-142 - 2004
- [j4]Ryoji Ishikawa, Takashi Hirayama, Goro Koda, Kensuke Shimizu:
New Three-Level Boolean Expression Based on EXOR Gates. IEICE Trans. Inf. Syst. 87-D(5): 1214-1222 (2004) - 2002
- [j3]Takashi Hirayama, Yasuaki Nishitani, Toru Sato:
A Faster Algorithm of Minimizing AND-EXOR Expressions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2708-2714 (2002) - [c2]Takashi Hirayama, Yasuaki Nishitani, Toru Sato:
A faster algorithm of minimizing AND-EXOR expressions. APCCAS (2) 2002: 293-298 - [c1]Ryoji Ishikawa, Tomonori Igarashi, Takashi Hirayama, Kensuke Shimizu:
Pseudocube-based expressions to enhance testability. APCCAS (2) 2002: 305-310
1990 – 1999
- 1999
- [j2]Ryoji Ishikawa, Goro Koda, Kensuke Shimizu, Takashi Hirayama:
Exor Decomposition with Common Variables and its Application to Multiple-Output Networks. J. Circuits Syst. Comput. 9(1-2): 83-97 (1999) - 1996
- [j1]Takashi Hirayama, Yasuaki Nishitani:
A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions. Syst. Comput. Jpn. 27(3): 18-25 (1996)
Coauthor Index
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