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Simone Casale Brunet
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- affiliation: École Polytechnique Fédérale de Lausanne, Switzerland
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2020 – today
- 2024
- [c48]Ünsal Öztürk, Utku Görkem Ertürk, Simone Casale-Brunet, Paolo Ribeca, Marco Mattavelli:
Efficient Neural Clustering and Compression of Strings Through Approximate Euclidean Embeddings of the Levenshtein Distance. DCC 2024: 575 - 2023
- [j9]Aurelien Bloch
, Simone Casale-Brunet, Marco Mattavelli:
Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System. J. Signal Process. Syst. 95(10): 1219-1229 (2023) - [c47]Junliang Luo
Unveiling social aggregation in the Decentraland metaverse platform. GoodIT 2023: 419-427 - [c46]Simone Casale Brunet, Marco Mattavelli, Leonardo Chiariglione:
Exploring the data of blockchain-based metaverses. MetaCom 2023: 109-113 - [i4]Simone Casale-Brunet, Leonardo Chiariglione, Marco Mattavelli:
Exploring the data of blockchain-based metaverses. CoRR abs/2308.16787 (2023) - [i3]Simone Casale-Brunet, Marco Mattavelli:
Secure-by-design smart contract based on dataflow implementations. CoRR abs/2309.17200 (2023) - 2022
- [c45]Simone Casale-Brunet, Paolo Ribeca, Claudio Alberti, Unsal Ozturk, Marco Mattavelli:
A Benchmark of Entropy Coders for the Compression of Genome Sequencing Data. DCC 2022: 1 - [c44]Unsal Ozturk, Simone Casale-Brunet, Paolo Ribeca, Marco Mattavelli:
MPEG-G Reference-Based Compression of Unaligned Reads Through Ultra-Fast Alignments. DCC 2022: 478 - [c43]Simone Casale-Brunet, Mirko Zichichi, Lee Hutchinson, Marco Mattavelli, Stefano Ferretti:
The impact of NFT profile pictures within social network communities. GoodIT 2022: 283-291 - [i2]Simone Casale-Brunet, Mirko Zichichi, Lee Hutchinson, Marco Mattavelli, Stefano Ferretti:
The impact of NFT profile pictures within social network communities. CoRR abs/2206.06443 (2022) - 2021
- [j8]Aurelien Bloch
Methodologies for Synthesizing and Analyzing Dynamic Dataflow Programs in Heterogeneous Systems for Edge Computing. IEEE Open J. Circuits Syst. 2: 769-781 (2021) - [c42]Aurelien Bloch, Simone Casale-Brunet, Marco Mattavelli:
Inter-actions parallel execution on GPU from high-level dataflow synthesis. ACSCC 2021: 1151-1155 - [c41]Simone Casale-Brunet, Paolo Ribeca, P. Doyle, Marco Mattavelli:
Networks of Ethereum Non-Fungible Tokens: A graph-based analysis of the ERC-721 ecosystem. Blockchain 2021: 188-195 - [c40]Aurelien Bloch
SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis. MCSoC 2021: 62-68 - [c39]Aurelien Bloch
Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms. MCSoC 2021: 69-76 - [i1]Simone Casale-Brunet, Paolo Ribeca, P. Doyle, Marco Mattavelli:
Networks of Ethereum Non-Fungible Tokens: A graph-based analysis of the ERC-721 ecosystem. CoRR abs/2110.12545 (2021) - 2020
- [j7]Anatoly Prihozhy
Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs. J. Signal Process. Syst. 92(10): 1091-1099 (2020)
2010 – 2019
- 2019
- [c38]Endri Bezati, Simone Casale Brunet, Romuald Mosqueron
An Heterogeneous Compiler of Dataflow Programs for Zynq Platforms. ICASSP 2019: 1537-1541 - 2018
- [j6]Malgorzata Michalska
High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs. IEEE Trans. Multi Scale Comput. Syst. 4(2): 127-140 (2018) - [j5]Simone Casale Brunet
Execution Trace Graph of Dataflow Process Networks. IEEE Trans. Multi Scale Comput. Syst. 4(3): 340-354 (2018) - [c37]Simone Casale Brunet, Thierry Schüpbach, Nicolas Guex
Towards in the Field Fast Pathogens Detection Using FPGAs. FPL 2018: 463-464 - [c36]Apostolos Modas, Simone Casale Brunet, Robert J. Stewart
Shared-variable Synchronization Approaches for Dynamic Data Flow Programs. SiPS 2018: 263-268 - [c35]Anatoly Prihozhy
Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines. SiPS 2018: 337-342 - 2017
- [j4]Endri Bezati
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4): 699-703 (2017) - [c34]Endri Bezati, Simone Casale Brunet, Marco Mattavelli:
Execution trace graph based interface synthesis of signal processing dataflow programs for heterogeneous MPSoCs. ACSSC 2017: 494-498 - [c33]Simone Casale Brunet, Endri Bezati, Aurelien Bloch
Profiling of dynamic dataflow programs on MPSoC multi-core architectures. ACSSC 2017: 504-508 - [c32]Malgorzata Michalska, Endri Bezati, Simone Casale Brunet, Marco Mattavelli:
Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms. EUSIPCO 2017: 1339-1343 - [c31]Simone Casale Brunet, Endri Bezati, Marco Mattavelli:
High level synthesis of Smith-Waterman dataflow implementations. ICASSP 2017: 1173-1177 - [c30]Simone Casale Brunet, Endri Bezati, Marco Mattavelli:
Design space exploration of dataflow-based Smith-Waterman FPGA implementations. SiPS 2017: 1-6 - 2016
- [j3]Massimo Canale, Simone Casale Brunet
Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques - Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies. J. Signal Process. Syst. 84(3): 371-381 (2016) - [j2]Carlo Sau
Automated Design Flow for Multi-Functional Dataflow-Based Platforms. J. Signal Process. Syst. 85(1): 143-165 (2016) - [c29]Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck:
High-level system synthesis and optimization of dataflow programs for MPSoCs. ACSSC 2016: 417-421 - [c28]Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck:
Trace-based manycore partitioning of stream-processing applications. ACSSC 2016: 422-426 - [c27]Malgorzata Michalska, Endri Bezati, Simone Casale Brunet, Marco Mattavelli:
A Partition Scheduler Model for Dynamic Dataflow Programs. ICCS 2016: 2287-2291 - [c26]Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli:
High-Precision Performance Estimation of Dynamic Dataflow Programs. MCSoC 2016: 101-108 - [c25]Simone Casale Brunet, Endri Bezati, Marco Mattavelli:
Programming Models and Methods for Heterogeneous Parallel Embedded Systems. MCSoC 2016: 289-296 - [c24]Malgorzata Michalska, J. J. Ahmad, Endri Bezati, Simone Casale Brunet, Marco Mattavelli:
Performance estimation of program partitions on multi-core platforms. PATMOS 2016: 1-8 - [c23]Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck:
High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms. SAMOS 2016: 227-234 - 2015
- [c22]Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli:
Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs. ICCS 2015: 1443-1452 - 2014
- [c21]Jörn W. Janneck, Gustav Cedersjö, Endri Bezati, Simone Casale Brunet:
Dataflow machines. ACSSC 2014: 1848-1852 - [c20]Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Massimo Canale, Jörn W. Janneck:
Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. DASIP 2014: 1-6 - [c19]Simone Casale Brunet, M. Wiszniewska, Endri Bezati, Marco Mattavelli, Jörn W. Janneck, Massimo Canale:
TURNUS: An open-source design space exploration framework for dynamic stream programs. DASIP 2014: 1-2 - [c18]Ab Al-Hadi Ab Rahman, Simone Casale Brunet, Claudio Alberti, Marco Mattavelli:
A methodology for optimizing buffer sizes of dynamic dataflow fpgas implementations. ICASSP 2014: 5003-5007 - [c17]Damien de Saint Jorre, Claudio Alberti, Marco Mattavelli, Simone Casale Brunet:
Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms. ICIP 2014: 2115-2119 - [c16]Jörn W. Janneck, Simone Casale Brunet, Marco Mattavelli:
Characterizing communication behavior of dataflow programs using trace analysis. ICSAMOS 2014: 44-50 - [c15]Carlo Sau
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case. ICSAMOS 2014: 59-66 - [c14]Massimo Canale, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck:
Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. SiPS 2014: 7-12 - 2013
- [j1]Simone Casale Brunet, Abdallah Elguindy, Endri Bezati, Richard Thavot, Ghislain Roquier, Marco Mattavelli, Jörn W. Janneck:
Methods to explore design space for MPEG RMC codec specifications. Signal Process. Image Commun. 28(10): 1278-1294 (2013) - [c13]Simone Casale Brunet, Endri Bezati, Claudio Alberti, Marco Mattavelli, Edoardo Amaldi, Jörn W. Janneck:
Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications. ACSSC 2013: 1796-1800 - [c12]Simone Casale Brunet, Marco Mattavelli, Claudio Alberti, Jörn W. Janneck:
Systems design space exploration by serial dataflow program execution. ACSSC 2013: 1805-1809 - [c11]Simone Casale Brunet, Marco Mattavelli, Claudio Alberti, Jörn W. Janneck:
Representing Guard Dependencies in Dataflow Execution Traces. CICSyN 2013: 291-295 - [c10]Simone Casale Brunet, Claudio Alberti, Marco Mattavelli, Jörn W. Janneck:
Turnus: A unified dataflow design space exploration framework for heterogeneous parallel systems. DASIP 2013: 47-54 - [c9]Ab Al-Hadi Ab Rahman, Simone Casale Brunet, Claudio Alberti, Marco Mattavelli:
Dataflow program analysis and refactoring techniques for design space exploration: MPEG-4 AVC/H.264 decoder implementation case study. DASIP 2013: 63-70 - [c8]Simone Casale Brunet, Endri Bezati, Claudio Alberti, Ghislain Roquier, Marco Mattavelli, Jörn W. Janneck, Jani Boutellier:
Design space exploration and implementation of RVC-CAL applications using the TURNUS framework. DASIP 2013: 341-342 - [c7]Massimo Canale, Simone Casale Brunet:
A Lego Mindstorms NXT experiment for Model Predictive Control education. ECC 2013: 2549-2554 - [c6]Simone Casale Brunet, Claudio Alberti, Marco Mattavelli, Jörn W. Janneck:
Design space exploration of high level stream programs on parallel architectures: A focus on the buffer size minimization and optimization problem. ISPA 2013: 738-743 - [c5]Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck:
TURNUS: A design exploration framework for dataflow system design. ISCAS 2013: 654 - [c4]Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck:
Buffer optimization based on critical path analysis of a dataflow program design. ISCAS 2013: 1384-1387 - [c3]Simone Casale Brunet, Endri Bezati, Claudio Alberti, Marco Mattavelli, Edoardo Amaldi, Jörn W. Janneck:
Partitioning and optimization of high level stream applications for multi clock domain architectures. SiPS 2013: 177-182 - 2012
- [c2]Ab Al-Hadi Ab Rahman, Richard Thavot, Simone Casale Brunet, Endri Bezati, Marco Mattavelli:
Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program. DASIP 2012: 1-8 - [c1]Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck:
Profiling of Dataflow Programs Using Post Mortem Causation Traces. SiPS 2012: 220-225
Coauthor Index
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last updated on 2024-10-07 22:19 CEST by the dblp team
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