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Chixiao Chen
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2020 – today
- 2024
- [j20]Yinglin Yang, Yunzhengmao Wang
, Tengyue Yi, Chixiao Chen, Qi Liu:
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration. Integr. 96: 102170 (2024) - [j19]Mengjie Li
SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros. IEEE J. Solid State Circuits 59(11): 3853-3865 (2024) - [j18]Bo Jiao, Lei Xu, Xinyu Yu, Haitao Yang, Haozhe Zhu
FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4156-4168 (2024) - [j17]Haozhe Zhu
Trident-CIM: A LUT-Based Compute-in-Memory Macro With Trident Read Bit-Line and Partial Product Pruning. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2544-2548 (2024) - [j16]Shiwei Liu
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 269-282 (2024) - [c55]Wenning Jiang, Yunbin Luo, Peizhe Li, Ji Guo, Chixiao Chen, Qi Liu:
A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration. CICC 2024: 1-2 - [c54]Jingyi Wang, Zhangcheng Huang
A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision. CICC 2024: 1-2 - [c53]Jiapei Zheng
CAMPER: Exploring the Potential of Content Addressable Memory for 3D Point Cloud Efficient Range Search. DAC 2024: 129:1-129:6 - [c52]Bu Chen
CEDAR: Computing-in-pixel Edge-aware Detection and Reconstruction Architecture for High-resolution 3D Imaging. DAC 2024: 217:1-217:6 - [c51]Hongyi Zhang, Haozhe Zhu, Siqi He, Mengjie Li, Chengchen Wang, Xiankui Xiong, Haidong Tian, Xiaoyang Zeng, Chixiao Chen:
ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test. DATE 2024: 1-6 - [c50]Mengjie Li
A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder. ISCAS 2024: 1-5 - [c49]Lizhou Wu, Haozhe Zhu, Siqi He, Jiapei Zheng, Chixiao Chen, Xiaoyang Zeng:
GauSPU: 3D Gaussian Splatting Processor for Real-Time SLAM Systems. MICRO 2024: 1562-1573 - 2023
- [j15]Wenning Jiang, Yan Zhu
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. IEEE J. Solid State Circuits 58(10): 2709-2721 (2023) - [c48]Siqi He, Hongyi Zhang, Mengjie Li, Haozhe Zhu, Chixiao Chen, Qi Liu, Xiaoyang Zeng:
Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation. AICAS 2023: 1-5 - [c47]Jiapei Zheng, Hao Jiang, Xinkai Nie, Zhangcheng Huang
TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network. DAC 2023: 1-6 - [c46]Jiangnan Yu
TPNoC: An Efficient Topology Reconfigurable NoC Generator. ACM Great Lakes Symposium on VLSI 2023: 77-82 - [c45]Hao Jiang, Jiapei Zheng, Yunzhengmao Wang
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. ISCAS 2023: 1-5 - [c44]Jie Liao, Bo Jiao, Jinshan Zhang, Shiwei Liu, Hao Jiang, Jun Tao, Wenning Jiang, Qi Liu, Lihua Zhang, Haozhe Zhu, Chixiao Chen:
A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. ISCAS 2023: 1-5 - [c43]Xinsheng Wang, Maosong Shi, Peizhe Li, Jianwei Liu, Zhangcheng Huang
A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier. ISCAS 2023: 1-5 - [c42]Shiwei Liu, Peizhe Li, Jinshan Zhang, Yunzhengmao Wang
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. ISSCC 2023: 250-251 - 2022
- [j14]Chixiao Chen
Design Challenges of Intrachiplet and Interchiplet Interconnection. IEEE Des. Test 39(6): 99-109 (2022) - [j13]Keji Zhou
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 846-857 (2022) - [j12]Qing Wan
2022 roadmap on neuromorphic devices and applications research in China. Neuromorph. Comput. Eng. 2(4): 42501 (2022) - [j11]Danfeng Zhai
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4944-4957 (2022) - [c41]Chen Mu, Yunzhengmao Wang
A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits. AICAS 2022: 222-225 - [c40]Junru Sheng, Peng Zhai, Zhiyan Dong, Xiaoyang Kang, Chixiao Chen, Lihua Zhang:
Curriculum Adversarial Training for Robust Reinforcement Learning. IJCNN 2022: 1-8 - [c39]Shunli Wang, Shuaibing Wang, Bo Jiao, Dingkang Yang
CA-SpaceNet: Counterfactual Analysis for 6D Pose Estimation in Space. IROS 2022: 10627-10634 - [c38]Xiaoling Yi, Jiangnan Yu, Zheng Wu, Xiankui Xiong, Dong Xu, Chixiao Chen, Jun Tao, Fan Yang:
NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models. ISCAS 2022: 2806-2810 - [c37]Xinru Jia, Haozhe Zhu, Yunzheng Wang
A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization. ISCAS 2022: 2816-2820 - [c36]Zheng Wu, Wuzhen Xie, Xiaoling Yi, Haitao Yang, Ruiyao Pu, Xiankui Xiong, Haidong Yao, Chixiao Chen, Jun Tao, Fan Yang:
An Automated Compiler for RISC-V Based DNN Accelerator. ISCAS 2022: 3097-3101 - [c35]Haozhe Zhu
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. ISSCC 2022: 1-3 - [i2]Shunli Wang, Dingkang Yang, Peng Zhai, Chixiao Chen, Lihua Zhang:
TSA-Net: Tube Self-Attention Network for Action Quality Assessment. CoRR abs/2201.03746 (2022) - [i1]Shunli Wang, Shuaibing Wang, Bo Jiao, Dingkang Yang, Liuzhen Su, Peng Zhai, Chixiao Chen, Lihua Zhang:
CA-SpaceNet: Counterfactual Analysis for 6D Pose Estimation in Space. CoRR abs/2207.07869 (2022) - 2021
- [j10]Yuefeng Cao
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 641-654 (2021) - [c34]Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang:
Advances in Continuous-time MASH ΔΣ Modulators. ASICON 2021: 1-4 - [c33]Bo Jiao, Jinshan Zhang, Yuanyuan Xie, Shunli Wang, Haozhe Zhu, Xiaoyang Kang, Zhiyan Dong, Lihua Zhang
A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA. ASP-DAC 2021: 13-14 - [c32]Bo Jiao, Haozhe Zhu
Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors. ACM Great Lakes Symposium on VLSI 2021: 241-246 - [c31]Jinshan Zhang, Bo Jiao, Yunzhengmao Wang, Haozhe Zhu
ALPINE: An Agile Processing-in-Memory Macro Compilation Framework. ACM Great Lakes Symposium on VLSI 2021: 333-338 - [c30]Jingying Zhang, Yang Zhao, Mingyi Chen, Chixiao Chen, Fan Ye, Liang Qi:
Self-coupled MASH Delta-Sigma Modulator with Zero Optimization. ISOCC 2021: 1-2 - [c29]Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren:
Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. ISOCC 2021: 246-247 - [c28]Shunli Wang, Dingkang Yang, Peng Zhai, Chixiao Chen, Lihua Zhang:
TSA-Net: Tube Self-Attention Network for Action Quality Assessment. ACM Multimedia 2021: 4902-4910 - [c27]Danfeng Zhai, Peizhe Li, Jiushan Zhang, Chixiao Chen, Fan Ye, Junyan Ren:
Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization. MWSCAS 2021: 292-296 - 2020
- [j9]Haozhe Zhu
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 283-294 (2020) - [j8]Liangjian Lyu
A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. Integr. 70: 51-59 (2020) - [c26]Shiwei Liu
XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping. AICAS 2020: 21-25 - [c25]Min Chen, Yimin Wu, Jingchao Lan, Fan Ye, Chixiao Chen, Junyan Ren:
A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network. APCCAS 2020: 205-208
2010 – 2019
- 2019
- [j7]Chixiao Chen
iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 346-357 (2019) - [c24]Liangjian Lyu
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. ASP-DAC 2019: 13-14 - [c23]Aili Wang, Chixiao Chen, Chuanjin Richard Shi:
A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time. CICC 2019: 1-4 - [c22]Tianli Zhang
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. ESSCIRC 2019: 189-192 - [c21]Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren:
A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. ESSCIRC 2019: 197-200 - 2018
- [j6]Chixiao Chen
OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 519-530 (2018) - [c20]Chixiao Chen, Huwan Peng, Xindi Liu, Hongwei Ding, Chuanjin Richard Shi:
Exploring the programmability for deep learning processors: from architecture to tensorization. DAC 2018: 15:1-15:6 - [c19]Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, Chuanjin Richard Shi:
iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS. ESSCIRC 2018: 170-173 - 2017
- [j5]Aili Wang
Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2284-2294 (2017) - [c18]Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu
OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators. ESSCIRC 2017: 259-262 - [c17]Hang Hu, Zemin Feng, Chixiao Chen, Fan Ye, Junyan Ren:
High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators. MWSCAS 2017: 1009-1012 - 2016
- [c16]Bingwei Jiang
A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network. A-SSCC 2016: 353-356 - [c15]Xiaolong Liu, Chixiao Chen, Junyan Ren, Howard C. Luong:
Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS. A-SSCC 2016: 357-360 - 2015
- [j4]Chixiao Chen, Jixuan Xiang, Jiang Fan, Xu Jun, Ye Fan, Junyan Ren:
A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators. IEICE Electron. Express 12(5): 20141143 (2015) - [j3]Chixiao Chen, Zemin Feng, Jun Xu, Fan Ye, Junyan Ren:
An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 721-725 (2015) - [c14]Zemin Feng, Jingjing Wang, Chixiao Chen, Jun Xu, Junyan Ren:
A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method. ASICON 2015: 1-4 - [c13]Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren:
100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. ASICON 2015: 1-4 - [c12]Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren:
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC 2015: 136-139 - 2014
- [c11]Chixiao Chen, Zemin Feng, Huabin Chen, Mingshuo Wang, Jun Xu, Fan Ye
A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier. ISCAS 2014: 2361-2364 - [c10]Guoxian Dai, Chixiao Chen, Shunli Ma, Fan Ye, Junyan Ren:
A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. ISCAS 2014: 2365-2368 - 2013
- [j2]Bei Yu, Chixiao Chen, Fan Ye, Junyan Ren:
A mixed sample-time error calibration technique in time-interleaved ADCs. IEICE Electron. Express 10(24): 20130882 (2013) - [j1]Zhenyu Wang, Mingshuo Wang, Weiru Gu, Chixiao Chen, Fan Ye, Junyan Ren:
A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2834-2844 (2013) - [c9]Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren:
A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. ASICON 2013: 1-4 - [c8]Zemin Feng, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren:
A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator. ASICON 2013: 1-4 - [c7]Yuzhong Xiao, Chixiao Chen, Rui Wei, Fan Jiang, Jun Xu, Junyan Ren:
A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers. ASICON 2013: 1-4 - [c6]Fan Jiang, Chixiao Chen, Yuzhong Xiao, Jun Xu, Junyan Ren:
Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers. MWSCAS 2013: 558-561 - 2012
- [c5]Yiwen Zhang, Xiaoshi Zhu, Chixiao Chen, Fan Ye, Junyan Ren:
A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation. APCCAS 2012: 128-131 - [c4]Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren:
A digitally calibrated current-steering DAC with current-splitting array. MWSCAS 2012: 278-281 - [c3]Chixiao Chen, ShengChang Cai, Jialiang Xu, Xiaoshi Zhu, Fan Ye, Junyan Ren:
An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling. MWSCAS 2012: 1100-1103 - 2011
- [c2]Qianqian Ha, Fan Ye, Chixiao Chen, Xiaoshi Zhu, Mingshuo Wang, Yu-Jing Lin, Ning Li, Junyan Ren:
A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application. ASICON 2011: 492-495 - [c1]Bei Yu, Chixiao Chen, Yu Zhu, Peng Zhang, Yiwen Zhang, Xiaoshi Zhu, Fan Ye, Junyan Ren:
A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation. A-SSCC 2011: 349-352
Coauthor Index
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