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Mikel Azkarate-askatsua
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- affiliation: IK4-IKERLAN, Arrasate/Mondragòn, Spain
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2020 – today
- 2021
- [j3]Irune Yarza
, Mikel Azkarate-askatsua
Legacy software migration based on timing contract aware real-time execution environments. J. Syst. Softw. 172: 110849 (2021) - 2020
- [c25]Carles Hernández, Jaume Abella
Workshop on High-performance Computing Platforms for Dependable Autonomous Systems. DSN Workshops 2020: xii - [c24]Irune Yarza
Static/dynamic real-time legacy software migration: a comparative analysis. RAPIDO 2020: 3:1-3:8
2010 – 2019
- 2019
- [c23]Kim Grüttner, Maher Fakih, Mikel Azkarate-askatsua
SAFEPOWER: Application of Power Management Techniques in SoCs for Safety-Relevant Systems. COINS 2019: 104-109 - 2018
- [j2]Irune Agirre
Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262. IEEE Trans. Reliab. 67(3): 1314-1327 (2018) - [c22]Tomaso Poggi
A Hypervisor Architecture for Low-Power Real-Time Embedded Systems. DSD 2018: 252-259 - [c21]Irune Yarza
Real-Time Capable Retargeting of Xilinx MicroBlaze Binaries using QEMU: A Feasibility Study. RAPIDO 2018: 3:1-3:8 - 2017
- [j1]Maher Fakih, Alina Lenz, Mikel Azkarate-askasua
SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems. Microprocess. Microsystems 52: 89-105 (2017) - [c20]Suzana Milutinovic
Software Time Reliability in the Presence of Cache Memories. Ada-Europe 2017: 233-249 - [c19]Ainara Bilbao
A railway safety and security concept for low-power mixed-criticality systems. INDIN 2017: 59-64 - [c18]Irune Agirre
On the tailoring of CAST-32A certification guidance to real COTS multicore architectures. SIES 2017: 1-8 - 2016
- [c17]Francisco J. Cazorla, Jaume Abella
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis. DSD 2016: 276-285 - [c16]Alina Lenz, Mikel Azkarate-Askasua Blazquez
SAFEPOWER Project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems. DSD 2016: 294-300 - [c15]Irune Agirre
Automotive Safety Concept Definition for Mixed-Criticality Integration on a COTS Multicore. SAFECOMP Workshops 2016: 273-285 - [c14]Enrique Díaz, Jaume Abella
Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis. WCET 2016: 1:1-1:11 - 2015
- [c13]Irune Agirre
A Safety Concept for a Railway Mixed-Criticality Embedded System Based on Multicore Partitioning. CIT/IUCC/DASC/PICom 2015: 1780-1787 - [c12]Irune Agirre
IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. DSD 2015: 677-684 - [c11]Asier Larrucea, Irune Agirre
Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning. FDL 2015: 130-137 - [c10]Jaume Abella
WCET analysis methods: Pitfalls and challenges on their trustworthiness. SIES 2015: 39-48 - 2011
- [c9]Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Mikel Azkarate-askasua
A (Fault-Tolerant)2 Scheduler for Real-Time HW Tasks. ARC 2011: 79-87 - [c8]Mikel Azkarate-askasua
Suitability of Hypervisor and MPSoC Architectures for the Execution Environment of an Integrated Embedded System. ISORC Workshops 2011: 19-24 - [c7]Mikel Azkarate-askasua, Xabier Iturbe, Imanol Martinez, Roman Obermaisser:
FI4SoC: A fault injection framework for transient fault effects in embedded MPSoCs. WISES 2011: 81-86 - 2010
- [c6]Xabier Iturbe
R3TOS: A reliable reconfigurable real-time operating system. AHS 2010: 99-104 - [c5]Xabier Iturbe
A Roadmap for Autonomous Fault-Tolerant Systems. DASIP 2010: 311-321 - [c4]Jon Pérez
Codesign and Simulated Fault Injection of Safety-Critical Embedded Systems Using SystemC. EDCC 2010: 221-229 - [c3]Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Imanol Martinez, Mikel Azkarate-askasua, Alicia Morales-Reyes:
Evolutionary Dynamic Allocation of Relocatable Modules onto Partially Damaged Xilinx FPGAs. ERSA 2010: 211-217 - [c2]Xabier Iturbe
ATB: Area-Time response Balancing algorithm for scheduling real-time hardware tasks. FPT 2010: 224-232
2000 – 2009
- 2009
- [c1]Xabier Iturbe
A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs. FPL 2009: 569-573
Coauthor Index
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