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Jawar Singh
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2020 – today
- 2024
- [j10]V. Bharath Sreenivasulu
, Aruna Kumari Neelam
Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications. IEEE Access 12: 7531-7539 (2024) - [j9]Meena Panchore
Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution. J. Electron. Test. 40(4): 487-496 (2024) - 2023
- [j8]V. Bharath Sreenivasulu, Aruna Kumari Neelam, Sekhar Reddy Kola
Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison. IEEE Access 11: 90421-90429 (2023) - [j7]Abhash Kumar
An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications. Circuits Syst. Signal Process. 42(5): 2828-2851 (2023) - [j6]Swati
Design and analysis of DDoS mitigating network architecture. Int. J. Inf. Sec. 22(2): 333-345 (2023) - [c32]Ankit Sirohi, Jawar Singh:
A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact. VLSI-SoC 2023: 1-6 - 2022
- [c31]Kota Nikhileswar, Sudhir Kumar, Jawar Singh, Dharmendra Muthuswamy:
A Framework for the Automation of Platform Validation for Use Cases of Wi-Fi. ICIT 2022: 1-6 - 2020
- [c30]Bhavye Sharma, Raju Halder
Blockchain-based Interoperable Healthcare using Zero-Knowledge Proofs and Proxy Re-Encryption. COMSNETS 2020: 1-6 - [i3]Abhash Kumar, Jawar Singh, Sai Manohar Beeraka, Bharat Gupta:
In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML Applications. CoRR abs/2005.09526 (2020)
2010 – 2019
- 2019
- [j5]Ankit Sirohi, Chitrakant Sahu
Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications. IEEE Access 7: 141810-141816 (2019) - [i2]Alok Kumar Kamal, Jawar Singh:
Ultra-Low Energy and High Speed LIF Neuron using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks. CoRR abs/1909.00669 (2019) - [i1]Md. Hasan Raza Ansari, Jawar Singh:
Improvement in Retention Time of Capacitorless DRAM with Access Transistor. CoRR abs/1910.03907 (2019) - 2017
- [c29]Nawaz Shafi
SiGe Source Charge Plasma TFET for Biosensing Applications. iNIS 2017: 93-98 - [c28]Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh
Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function. ISVLSI 2017: 609-614 - [c27]Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh
Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FET. ISVLSI 2017: 665-670 - 2016
- [c26]Chaitanya Maradana, Jawar Singh
Proposal of Heterogate Technique for Performance Enhancement of DM-TFET. iNIS 2016: 118-123 - [c25]Meena Panchore, Jawar Singh
Compact Behavioral Modeling and Time Dependent Performance Degradation Analysis of Junction and Doping Free Transistors. iNIS 2016: 194-199 - [c24]Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Jawar Singh
Secure Multi-key Generation Using Ring Oscillator Based Physical Unclonable Function. iNIS 2016: 200-205 - [c23]Muhammad Khalid
Memristor Crossbar-Based Pattern Recognition Circuit Using Perceptron Learning Rule. iNIS 2016: 236-239 - 2015
- [j4]Sunil Kumar Pandey, Jawar Singh
A low power and high gain CMOS LNA for UWB applications in 90 nm CMOS process. Microelectron. J. 46(5): 390-397 (2015) - [c22]Kanchan Cecil, Jawar Singh
Performance Enhancement of Dopingless Tunnel-FET Based on Ge-Source with High-k. iNIS 2015: 19-22 - [c21]Lokesh Kumar Bramhane, Jawar Singh
Extended Base Schottky-Collector Bipolar Charge Plasma Transistor. iNIS 2015: 137-140 - 2014
- [c20]Anup Shrivastava
Dual-sided doped memristor and it's SPICE modelling for improved electrical properties. ISQED 2014: 317-322 - [c19]Komal Singh, Chitrakant Sahu
Linearly separable pattern classification using memristive crossbar circuits. ISQED 2014: 323-329 - [c18]Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh
Realization of efficient RF energy harvesting circuits employing different matching technique. ISQED 2014: 754-761 - [c17]Deep Kishore Parsediya
Modeling and simulation of variable thickness based stepped MEMS cantilever designs for biosensing and pull-in voltage optimization. VDAT 2014: 1-2 - 2013
- [j3]Jawar Singh
A highly reliable NBTI Resilient 6T SRAM cell. Microelectron. Reliab. 53(4): 565-572 (2013) - [c16]Anup Shrivastava
Dual sided doped memristor and it's mathematical modelling. ICECS 2013: 49-51 - [c15]Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh
An Efficient RF Energy Harvester with Tuned Matching Circuit. VDAT 2013: 138-145 - 2012
- [j2]Saraju P. Mohanty, Jawar Singh
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. Integr. 45(1): 33-45 (2012) - [c14]G. K. Reddy, Kapil Jainwal, Jawar Singh
Process variation tolerant 9T SRAM bitcell design. ISQED 2012: 493-497 - 2010
- [c13]Jawar Singh, Krishnan Ramakrishnan, Saurabh Mookerjea, Suman Datta, Narayanan Vijaykrishnan, Dhiraj K. Pradhan:
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications. ASP-DAC 2010: 181-186 - [c12]Andrew J. Ricketts, Jawar Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, Dhiraj K. Pradhan:
Investigating the impact of NBTI on different power saving cache strategies. DATE 2010: 592-597 - [c11]Jawar Singh
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. ISQED 2010: 131-138
2000 – 2009
- 2009
- [b1]Jawar Singh:
Robust power aware SRAM bitcell designs. University of Bristol, UK, 2009 - [c10]Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew:
Single ended 6T SRAM with isolated read-port for low-power embedded systems. DATE 2009: 917-922 - [c9]Jawar Singh
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. VLSI Design 2009: 307-312 - 2008
- [j1]Jawar Singh
A single ended 6T SRAM cell design for ultra-low-voltage applications. IEICE Electron. Express 5(18): 750-755 (2008) - [c8]Jimson Mathew, Jawar Singh
Fault Tolerant Reversible Finite Field Arithmetic Circuits. IOLTS 2008: 188-189 - [c7]Jimson Mathew, Jawar Singh
Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS 2008: 1684-1687 - [c6]Jawar Singh
A nano-CMOS process variation induced read failure tolerant SRAM cell. ISCAS 2008: 3334-3337 - [c5]Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan:
Pseudo parallel architecture for AES with error correction. SoCC 2008: 187-190 - [c4]Jawar Singh
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. SoCC 2008: 243-246 - [c3]Jawar Singh
Failure analysis for ultra low power nano-CMOS SRAM under process variations. SoCC 2008: 251-254 - 2007
- [c2]Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan:
Single Event Upset Detection and Correction. ICIT 2007: 13-18 - [c1]Babita R. Jose, P. Mythili, Jawar Singh, Jimson Mathew:
A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards. ICIT 2007: 127-132
Coauthor Index
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last updated on 2024-11-07 21:36 CET by the dblp team
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