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Jong-Kee Kwon
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2010 – 2019
- 2018
- [j13]Chul Kim
, Chang-Seok Chae, Young-Sub Yuk, Chris M. Thomas, Yi-Gyeong Kim, Jong-Kee Kwon, Sohmyung Ha
A 500-MHz Bandwidth 7.5-mVpp Ripple Power-Amplifier Supply Modulator for RF Polar Transmitters. IEEE J. Solid State Circuits 53(6): 1653-1665 (2018) - 2012
- [j12]Sewan Heo
Adaptive Energy Management System Based on Low-Power Microcontroller with Energy harvesting at Maximum Power. J. Circuits Syst. Comput. 21(8) (2012) - [j11]Young-Deuk Jeon, Jae-Won Nam
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture. IEEE Trans. Circuits Syst. II Express Briefs 59-II(11): 741-745 (2012) - 2011
- [j10]Sang-Hun Yoon, Daegun Oh, Jong-Wha Chong, Tae Moon Roh
A Novel Timing Estimation Method for Chirp-Based Systems. IEICE Trans. Commun. 94-B(12): 3607-3609 (2011) - [j9]Sang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, Seung-Tak Ryu:
A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction. IEEE J. Solid State Circuits 46(8): 1881-1892 (2011) - [j8]Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Jong-Kee Kwon:
A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique. Microelectron. J. 42(11): 1225-1230 (2011) - [j7]Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon:
A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications. Microelectron. J. 42(12): 1335-1342 (2011) - [c13]Jin-Seon Kim, Tae-In Kwon, Gil-Cho Ahn, Yi-Gyeong Kim, Jong-Kee Kwon:
A ΔΣ ADC using 4-bit SAR type quantizer for audio applications. ISOCC 2011: 73-75 - [c12]Jae-Won Nam, Young-Deuk Jeon, Seok-Ju Yun, Tae Moon Roh, Jong-Kee Kwon:
A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS. ISOCC 2011: 405-407 - 2010
- [j6]Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 502-506 (2010) - [c11]Sang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, Seung-Tak Ryu:
A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction. CICC 2010: 1-4 - [c10]Young-Deuk Jeon, Young-Kyun Cho, Jae-Won Nam
A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS. CICC 2010: 1-4 - [c9]Chul Kim, Chang-Seok Chae, Young-sub Yuk, Yi-Gyeong Kim, Jong-Kee Kwon, Gyu-Hyeong Cho:
A 105dB-gain 500MHz-bandwidth 0.1Ω-output-impedance amplifier for an amplitude modulator in 65nm CMOS. ISSCC 2010: 88-89
2000 – 2009
- 2009
- [j5]Yong-Seo Koo, Kwi-Dong Kim, Jong-Kee Kwon:
ESD protection circuit with low triggering voltage and fast turn-on using substrate-triggered technique. IEICE Electron. Express 6(8): 467-471 (2009) - [j4]Hyungdong Roh, Hyoungjoong Kim, Youngkil Choi, Jeongjin Roh
A 0.6-V Delta-Sigma Modulator With Subthreshold-Leakage Suppression Switches. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 825-829 (2009) - [c8]Jae-Won Nam
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS. ESSCIRC 2009: 468-471 - 2008
- [j3]Jeongjin Roh
A 0.9-V 60-µW 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range. IEEE J. Solid State Circuits 43(2): 361-370 (2008) - [c7]Yi-Gyeong Kim, Min-Hyung Cho, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim:
A 105.5 dB, 0.49 mm2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWA. CICC 2008: 503-506 - 2007
- [j2]Seung-Chul Lee, Young-Deuk Jeon, Jong-Kee Kwon, Jongdae Kim:
A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications. IEEE J. Solid State Circuits 42(12): 2688-2695 (2007) - [c6]Young-Deuk Jeon, Seung-Chul Lee, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim:
A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS. ISSCC 2007: 456-615 - [c5]Seung-Chul Lee, Young-Deuk Jeon, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim, Jeong-Woong Moon, Woo-Yol Lee:
A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications. ISSCC 2007: 458-615 - 2006
- [j1]Seung-Chul Lee, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim, Seung-Hoon Lee:
A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-channel pipeline ADC without channel mismatch calibration. IEEE J. Solid State Circuits 41(7): 1596-1605 (2006) - [c4]Ja-Yol Lee, Kwi-Dong Kim, Jong-Kee Kwon, Seung-Chul Lee, Jongdae Kim, Sang-Heung Lee:
A 3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN Applications. CICC 2006: 377-380 - [c3]Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon:
A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications. CICC 2006: 497-500 - 2005
- [c2]Jun-Gi Jo, Changsik Yoo, Chun-Seok Jeong, Chan-Young Jeong, Mi-Young Lee, Jong-Kee Kwon:
A 1.2V, 10MHz, low-pass Gm-C filter with Gm-cells based on triode-biased MOS and passive resistor in 0.13μm CMOS technology. CICC 2005: 195-198 - [c1]Seung-Chul Lee, Gyu-Hyun Kim, Jong-Kee Kwon, Jongdae Kim, Seung-Hoon Lee:
Offset and dynamic gain-mismatch reduction techniques for 10b 200ms/s parallel pipeline ADCs. ESSCIRC 2005: 531-534
Coauthor Index
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