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Marco Lanuzza
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- affiliation: University of Calabria, Department of Computer Engineering, Cosenza, Italy
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2020 – today
- 2024
- [j47]Esteban Garzón
, Robert Hanhan
FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access 12: 13923-13943 (2024) - 2023
- [j46]Luigi Fassio
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V. IEEE Access 11: 3584-3596 (2023) - [j45]Esteban Garzón
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. IEEE Access 11: 16812-16819 (2023) - [j44]Hanan Marinberg, Esteban Garzón
Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach. IEEE Access 11: 94885-94897 (2023) - [j43]Tatiana Moposita
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. IEEE Access 11: 144084-144094 (2023) - [j42]Esteban Garzón
AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 408-421 (2023) - [j41]Tatiana Moposita
Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1254-1258 (2023) - [j40]Ariana Musello
XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1259-1263 (2023) - [j39]Esteban Garzón
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3867-3871 (2023) - [c44]Esteban Garzón
STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. LASCAS 2023: 1-4 - 2022
- [j38]Esteban Garzón
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. IEEE Access 10: 28080-28093 (2022) - [j37]Benjamin Zambrano
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification. IEEE Access 10: 94417-94430 (2022) - [j36]Massimo Vatalaro
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm. IEEE J. Solid State Circuits 57(8): 2509-2520 (2022) - [j35]Esteban Garzón
AIDA: Associative In-Memory Deep Learning Accelerator. IEEE Micro 42(6): 67-75 (2022) - [j34]Benjamin Zambrano
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 749-753 (2022) - [c43]Massimo Vatalaro, Raffaele De Rose, Marco Lanuzza
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider. ICECS 2022 2022: 1-4 - [c42]Robert Hanhan
EDAM: edit distance tolerant approximate matching content addressable memory. ISCA 2022: 495-507 - [c41]Esteban Garzón
A RISC-V-based Research Platform for Rapid Design Cycle. ISCAS 2022: 2614-2615 - [c40]Esteban Garzón
Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. LASCAS 2022: 1-4 - [c39]Tatiana Moposita, Lionel Trojman, Felice Crupi, Marco Lanuzza
Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks. LASCAS 2022: 1-4 - [i4]Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Adam Teman, Marco Lanuzza:
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. CoRR abs/2204.09395 (2022) - [i3]Raffaele De Rose, Tommaso Zanotti, Francesco Maria Puglisi, Felice Crupi, Paolo Pavan, Marco Lanuzza
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing. CoRR abs/2205.09388 (2022) - [i2]Benjamin Zambrano, Esteban Garzón, Sebastiano Strangio, Giuseppe Iannaccone, Marco Lanuzza:
A 0.6V$-$1.8V Compact Temperature Sensor with 0.24°C Resolution, $\pm$1.4°C Inaccuracy and 1.06nJ per Conversion. CoRR abs/2209.00815 (2022) - 2021
- [j33]Luigi Fassio, Longyang Lin
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW. IEEE J. Solid State Circuits 56(10): 3134-3144 (2021) - [j32]Luigi Fassio, Francesco Settino
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1393-1397 (2021) - [j31]Luigi Fassio, Longyang Lin
A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3038-3042 (2021) - [j30]Esteban Garzón
Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1319-1324 (2021) - [c38]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy. ESSCIRC 2021: 343-346 - [c37]Netanel Shavit, Inbal Stanger, Ramiro Taco
Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET. ISCAS 2021: 1 - [c36]Inbal Stanger, Netanel Shavit, Ramiro Taco
Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. ISCAS 2021: 1 - [c35]Ricardo Escobar, Luis-Miguel Prócel
High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. LASCAS 2021: 1-4 - [c34]Lionel Trojman, David Rivadeneira, Marco Villegas, Eliana Acurio
RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies. LASCAS 2021: 1-4 - [c33]Carmelo Felicetti, Marco Lanuzza
Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC. SmartIoT 2021: 229-236 - [i1]Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits:
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. CoRR abs/2111.09747 (2021) - 2020
- [j29]Esteban Garzón
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework. Integr. 71: 56-69 (2020) - [j28]Inbal Stanger
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1639-1643 (2020) - [c32]Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish:
Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. ISCAS 2020: 1-5 - [c31]Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish:
Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. ISCAS 2020: 1-5 - [c30]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j27]Raffaele De Rose
Double-precision Dual Mode Logic carry-save multiplier. Integr. 64: 71-77 (2019) - [j26]Ramiro Taco
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. IEEE J. Solid State Circuits 54(2): 560-568 (2019) - [c29]Marco Lanuzza
Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers. ASICON 2019: 1-4 - [c28]Esteban Garzón
Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory. ICECS 2019: 123-124 - [c27]Marco Lanuzza
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops. ICECS 2019: 158-161 - [c26]Carmelo Felicetti
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions. IDCS 2019: 294-305 - [c25]Ramiro Taco
Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI. ISCAS 2019: 1 - [c24]Esteban Garzón
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. SMACD 2019: 85-88 - 2018
- [j25]Felice Crupi
A portable class of 3-transistor current references with low-power sub-0.5 V operation. Int. J. Circuit Theory Appl. 46(4): 779-795 (2018) - [j24]Raffaele De Rose
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 1086-1095 (2018) - [c23]Raffaele De Rose, Felice Crupi, Maksym Paliy
Design of a 3T current reference for low-voltage, low-power operation. ICICDT 2018: 13-16 - [c22]Noemi Guerra, Raffaele De Rose, Marco Guevara
Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations. RTSI 2018: 1-4 - 2017
- [j23]Raffaele De Rose
A physical unclonable function based on a 2-transistor subthreshold voltage divider. Int. J. Circuit Theory Appl. 45(2): 260-273 (2017) - [j22]Marco Lanuzza
Low energy/delay overhead level shifter for wide-range voltage conversion. Int. J. Circuit Theory Appl. 45(11): 1637-1646 (2017) - [j21]Marco Lanuzza
An Ultralow-Voltage Energy-Efficient Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs 64-II(1): 61-65 (2017) - [c21]Raffaele De Rose, Domenico Albano, Felice Crupi, Marco Lanuzza
Design of a sub-1-V nanopower CMOS current reference. ECCTD 2017: 1-4 - [c20]Raffaele De Rose
A variation-aware simulation framework for hybrid CMOS/spintronic circuits. ISCAS 2017: 1-4 - [c19]Ramiro Taco
Evaluation of Dual Mode Logic in 28nm FD-SOI technology. ISCAS 2017: 1-4 - [c18]Raffaele De Rose
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework. SMACD 2017: 1-4 - 2016
- [c17]Ramiro Taco
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology. ISCAS 2016: 41-44 - 2015
- [j20]Domenico Albano, Marco Lanuzza
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. Int. J. Circuit Theory Appl. 43(11): 1523-1540 (2015) - [j19]Marco Lanuzza
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 388-391 (2015) - [j18]Ramiro Taco
Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits. VLSI Design 2015: 540482:1-540482:10 (2015) - 2014
- [j17]Raffaele De Rose
Designing Dynamic Carry Skip Adders: Analysis and Comparison. Circuits Syst. Signal Process. 33(4): 1019-1034 (2014) - [j16]Pasquale Corsonello
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. Int. J. Circuit Theory Appl. 42(1): 65-70 (2014) - [j15]Fabio Frustaci
Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. Int. J. Circuit Theory Appl. 42(5): 452-467 (2014) - [j14]Stefania Perri
Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. Int. J. Circuit Theory Appl. 42(7): 731-743 (2014) - [j13]Pasquale Corsonello
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1456-1464 (2014) - [c16]Marco Lanuzza
Improving speed and power characteristics of pulse-triggered flip-flops. LASCAS 2014: 1-4 - [c15]Marco Lanuzza
Dynamic gate-level body biasing for subthreshold digital design. LASCAS 2014: 1-4 - 2013
- [j12]Marco Lanuzza
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops. J. Low Power Electron. 9(4): 445-451 (2013) - 2012
- [j11]Fabio Frustaci
Energy-efficient single-clock-cycle binary comparator. Int. J. Circuit Theory Appl. 40(3): 237-246 (2012) - [j10]Marco Lanuzza
Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. 52(8): 1679-1689 (2012) - [j9]Marco Lanuzza
Low-Power Level Shifter for Multi-Supply Voltage Designs. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 922-926 (2012) - 2010
- [j8]Sohan Purohit, Marco Lanuzza
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. J. Low Power Electron. 6(4): 469-481 (2010) - [j7]Marco Lanuzza
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. ACM Trans. Reconfigurable Technol. Syst. 4(1): 8:1-8:22 (2010) - [c14]Sumit Kansal, Marco Lanuzza
Impact of Random Process Variations on Different 65nm SRAM Cell Topologies. ICETET 2010: 703-706 - [c13]Fabio Frustaci
A new low-power high-speed single-clock-cycle binary comparator. ISCAS 2010: 317-320 - [c12]Marco Lanuzza
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI 2010: 458-459 - [c11]Marco Lanuzza
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS 2010: 180-189
2000 – 2009
- 2009
- [j6]Fabio Frustaci
Low-power split-path data-driven dynamic logic. IET Circuits Devices Syst. 3(6): 303-312 (2009) - [j5]Sohan Purohit, Marco Lanuzza
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electron. 5(3): 326-338 (2009) - [j4]Fabio Frustaci
Designing High-Speed Adders in Power-Constrained Environments. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 172-176 (2009) - [c10]Marco Lanuzza
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. ARC 2009: 74-84 - [c9]Sohan Purohit, Martin Margala
New performance/power/area efficient, reliable full adder design. ACM Great Lakes Symposium on VLSI 2009: 493-498 - [c8]Fabio Frustaci
A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder. PATMOS 2009: 357-366 - [c7]Sohan Purohit, Marco Lanuzza
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design 2009: 45-50 - 2008
- [c6]Marco Lanuzza
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS 2008: 297-306 - 2007
- [c5]Marco Lanuzza
A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS 2007: 119-126 - [c4]Pasquale Corsonello
Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD 2007: 383-389 - [c3]Marco Lanuzza
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. SAMOS 2007: 159-168 - 2006
- [j3]Pasquale Corsonello
Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Technol. 16(1): 114-128 (2006) - 2005
- [b1]Marco Lanuzza:
Progetto e realizzazione VLSI di circuiti aritmetici ottimizzati per applicazioni multimediali. University of Calabria, Italy, 2005 - [j2]Stefania Perri
A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsystems 29(8-9): 381-391 (2005) - [c2]Marco Lanuzza
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL 2005: 13-18 - [c1]Marco Lanuzza, Martin Margala, Pasquale Corsonello:
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. ISLPED 2005: 161-166 - 2004
- [j1]Stefania Perri
Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 995-999 (2004)
Coauthor Index
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