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Koh Johguchi
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2020 – today
- 2023
- [c12]Yuichiro Ichimura, Kenta Goto, Koh Johguchi:
Temperature Sensor Circuit for a Wearable Perspiration Monitoring System. ISDCS 2023: 1-4 - [c11]Kaede Kano, Koh Johguchi:
Photodiode and Analog-Front-End Circuit Design for Wearable Vital Sensing System with Fiber-Bragg-Grating Sensor. ISDCS 2023: 1-4 - 2020
- [c10]Koh Johguchi:
A Smart Hybrid Solid-State-Drive Storage System based on Nonvolatile Storage-Class-Memories : Device, Circuit Design and Architecture. ISDCS 2020: 1-2
2010 – 2019
- 2019
- [c9]Tera Sakata, Yusuke Mitani, Kousuke Miyaji, Satoshi Kaneko, Takaharu Uekura, Hidetoshi Taki, Hideya Momose, Koh Johguchi:
A CMOS Integrated Sweat Monitoring System for Medical Applications. ISDCS 2019: 1-2 - 2018
- [c8]Hassan Arafat, Ryohei Shimizu, Koh Johguchi:
Hierarchial Hybrid Solid State Drive. TENCON 2018: 1516-1519 - 2016
- [j9]Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi, Hirofumi Takishita, Ken Takeuchi:
Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2208-2219 (2016) - 2014
- [j8]Koh Johguchi, Toru Egami, Kousuke Miyaji, Ken Takeuchi:
A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories. IEICE Trans. Electron. 97-C(4): 342-350 (2014) - [j7]Koh Johguchi, Kasuaki Yoshioka, Ken Takeuchi:
NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance. IEICE Trans. Electron. 97-C(4): 351-359 (2014) - [j6]Chao Sun, Kousuke Miyaji, Koh Johguchi, Ken Takeuchi:
A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(2): 382-392 (2014) - [j5]Chao Sun, Tomoko Ogura Iwasaki, Takahiro Onagi, Koh Johguchi, Ken Takeuchi:
Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2360-2369 (2014) - [c7]Chao Sun, Ayumi Soga, Takahiro Onagi, Koh Johguchi, Ken Takeuchi:
A workload-aware-design of 3D-NAND flash memory for enterprise SSDs. ISQED 2014: 554-561 - 2013
- [c6]Chao Sun, Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Ken Takeuchi:
Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression. ASP-DAC 2013: 81-82 - 2012
- [c5]Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Chao Sun, Ken Takeuchi:
x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression. VLSIC 2012: 134-135 - 2011
- [j4]Norio Sadachika, Shu Mimura, Akihiro Yumisaki, Koh Johguchi, Akihiro Kaya, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design. IEICE Trans. Electron. 94-C(3): 361-367 (2011) - [c4]Teruyoshi Hatanaka, Koh Johguchi, Ken Takeuchi:
A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives. 3DIC 2011: 1-4 - 2010
- [j3]Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika:
Measurement-Based Ring Oscillator Variation Analysis. IEEE Des. Test Comput. 27(5): 6-13 (2010)
2000 – 2009
- 2007
- [j2]Koh Johguchi, Yuya Mukuda, Ken-ichi Aoyama, Hans Jürgen Mattausch, Tetsushi Koide:
A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin. IEICE Electron. Express 4(2): 21-25 (2007) - [j1]Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka:
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Trans. Electron. 90-C(11): 2157-2160 (2007) - [c3]Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide:
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. ESSCIRC 2007: 320-323 - 2006
- [c2]Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa:
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS 2006: 1297-1300 - 2003
- [c1]Zhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka:
A novel hierarchical multi-port cache. ESSCIRC 2003: 405-408
Coauthor Index
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