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Journal of Multiple-Valued Logic, Volume 13
Volume 13, Numbers 1-2, 2007
- Vilém Vychodil:
Direct Limits and Reduced Products of Algebras with Fuzzy Equalities. 1-28 - Andrew Schumann:
p-Adic Multiple-Validity and p-Adic Valued Logical Calculi. 29-60 - David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat:
Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. 61-78 - Manuel Abad, J. Patricio Díaz Varela, Laura A. Rueda, Ana Maria Suardíaz:
The Lattice of Subvarieties of Monadic n-valued Loukasiewicz-Moisil Algebras. 79-88 - Chi-Yung Lee, Cheng-Jian Lin, Yung-Chi Hsu:
A Parametric Fuzzy CMAC Model with Hybrid Evolutionary Learning Algorithms. 89-114 - Ivan Chajda, Shelly L. Wismath:
Constructions on P-Choice Algebras. 115-126 - Stathis Livadas:
Indiscernibility in Topologies of Finitely Observable Properties. 127-144 - Wei Yang, Luis Rueda, Alioune Ngom:
On Finding the Best Parameters of Fuzzy k-Means for Clustering Microarray Data. 145-178 - Rajab Ali Borzooei, Mahmood Bakhshi:
Lattice Structure on Weak Hyper BCK-ideals. 179-190 - Ali Khazamipour, Katarzyna Radecka:
Adiabatic Implementation of Reversible Logic Circuits in CMOS Technology. 191-216
Volume 13, Number 3, 2007
- Svetlana N. Yanushkevich, Vlad P. Shmerko:
Introduction to the Special Issue: Nano MVL Structures. 217-234 - Erik Curtis, Marek A. Perkowski:
Minimization of Ternary Reversible Logic Cascades Using a Universal Subset of Generalized Ternary Gates. 235-248 - Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi:
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. 249-266 - Seiya Kasai, Tatsuya Nakamura, Yuta Shiratori:
Multiple Path Switching Device Utilizing Size-Controlled Nano-Schottky Wrap Gates for MDD-Based Logic Circuits. 267-277
Volume 13, Numbers 4-6, 2007
- Claudio Moraga, Milena Stankovic, Suzana Stojkovic:
Characterization of Ternary Cofactors in the Spectral Domain. 279-294 - Dan A. Simovici:
On Generalized Entropy and Entropic Metrics. 295-320 - Patrik Eklund, Maria A. Galán:
The Rough Powerset Monad. 321-334 - Anna Zamansky, Arnon Avron:
Effective Non-deterministic Semantics for First-order LFIs. 335-352 - Hajime Machida, Michael Pinsker:
Some Polynomials Generating Minimal Clones. 353-366 - Boris A. Romov:
Restriction-closed Hyperclones. 367-378 - Bogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba:
Family of Fastest Linearly Independent Transforms over GF(3): Generation, Relations, and Hardware Implementation. 379-396 - Viorica Sofronie-Stokkermans, Carsten Ihlemann:
Automated Reasoning in Some Local Extensions of Ordered Structures. 397-414 - Lucien Haddad, Dietlinde Lau:
Some Criteria for Partial Sheffer Functions in k-valued Logic. 415-446 - Krzysztof S. Berezowski, Sarma B. K. Vrudhula:
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. 447-466 - Radomir S. Stankovic, Jaakko Astola:
Interpretations of the Sampling Theorem in Multiple-Valued Logic. 467-486 - Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams. 487-502 - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions. 503-520 - Dragan Jankovic, Radomir S. Stankovic, Claudio Moraga:
Implementation Complexity of Algorithms for Optimization of Galois Field Expressions for Multiple-Valued Functions. 521-536 - D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton:
QMDD Minimization Using Sifting for Variable Reordering. 537-552 - Tasuku Ito, Michitaka Kameyama:
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. 553-568 - Yasushi Yuminaka, Kazuyoshi Yamamura:
Equalization Techniques for Multiple-Valued Data Transmission and Their Application. 569-582 - Mozammel H. A. Khan, Marek A. Perkowski:
GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits. 583-604 - Igor N. Aizenberg, Claudio Moraga:
The Genetic Code as a Function of Multiple-Valued Logic Over the Field of Complex Numbers and its Learning using Multilayer Neural Network Based on Multi-Valued Neurons. 605-618 - Nobuaki Okada, Michitaka Kameyama:
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. 619-632
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