default search action
Microprocessing and Microprogramming, Volume 38
Volume 38, Numbers 1-5, September 1993
- Mateo Valero, Jordi Cortadella
, Antonio González:
Chairmen's introduction. - Manuel Silva Suárez, José Manuel Colom:
Petri Nets applied to the modelling and analysis of computer architecture problems. 1-11 - Lotfi A. Zadeh:
Fuzzy logic, neural networks and soft computing. 13 - José A. B. Fortes:
Matching algorithms and architectures. 15 - Vincent Néri, Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble:
Hardware features of the static communication network of a parallel architecture. 19-24 - Janusz Sosnowski
Fault tolerant multiple-bus interconnection networks. 25-32 - Cruz Izu
Experimental evaluation of Mad Postman bidimensional routing networks. 33-41 - Klaus Waldschmidt:
Processor architecture I. 43-44 - Henk Corporaal:
Evaluating transport triggered architectures for scalar applications. 45-52 - Henk Corporaal, Paul van der Arend:
Move32int, a sea of gates realization of a high performance transport triggered architecture. 53-60 - Peter Pfahler, Christof Nagel, Franz-Josef Rammig, Uwe Kastens:
Design of a VLIW architecture constructed from standard RISC chips: A case study of hardware/software codesign. 61-68 - Werner Grass:
Session A3: System specification I. 69 - Stefano Antoniazzi, Alessandro Balboni, William Fornaciari
X-Nets: A visual formalism for system specification and analysis. 71-78 - Chris Ho-Stuart, Hussein Zedan, Ming Fang:
Automated support for the formal specification and design of real-time systems. 79-86 - Klaas Brink, Ronald Huijsman, Jan van Katwijk:
SEAL A simple language for prototyping action-event specifications. 87-95 - Peter Milligan:
Distributed memory management. 97-98 - Dimitris Lioupis, Nikos Kanellopoulos, Michalis Stefanidakis:
The memory hierarchy of the CHESS computer. 99-107 - Vincent Habchi, Ulrich Finger, Ciaran O'Donnell:
Some practical considerations for the implementer of the SCI network. 109-118 - Montse Peiron, Mateo Valero
Conflict-free access to streams in multiprocessor systems. 119-130 - Jordi Cortadella
Session B2: Processor Architecture II. 131 - Edil S. T. Fernandes, Fernando M. B. Barbosa, David M. Simpson:
Evaluating the Cost of conditional branches on the performance of superscalar machines. 133-140 - Michael Schäfers:
Branch optimization of the TOOBSIE2 RISC-processor and classification. 141-147 - Júlio S. Aude, Ernesto P. Lopes, Mario F. Martins, S. B. Pinto:
Arco: A cost-effective and flexible hardware maze router. 149-159 - Constantinos V. Papadopoulos, Abul Habbas el Zahni:
Protection and routing algorithms for network management : The case of transmission networks. 163-170 - Luís Moura Silva, João Gabriel Silva:
DIP : Distributed Diagnosis Protocol. 171-178 - S. Allegra, M. Annunziata, F. Cesaroni, C. Lunadei:
PLANNER 4: A simulator to design packet switching data network. 179-186 - Péter Kacsuk:
Parallel software engineering. 187-188 - B. Moisan, Yves Duthen, René Caubet:
Tools for object-oriented SPMD programming. 189-196 - Manuel I. Capel, José M. Troya, A. Palma:
Distributed active objects: A methodological proposal and tool for distributed programming with transputer systems. 197-204 - Wouter Joosen, Stijn Bijnens, Pierre Verbaeten:
A reusable load balancer for parallel search problems. 205-212 - Jean Paul Calvez, Olivier Pasquier:
Real-time behavior monitoring for multi-processor systems. 213-220 - István Erényi:
VLSI testing and testability. 221 - Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser, Raul Camposano:
Fault behavior and testability of asynchronous CMOS circuits. 223-228 - Cristiana Bolchini
FSM fault models impact on test performances. 229-236 - K. Ivinskis:
Redundancy analysis and removal for VLSI ASIC's. 237-243 - Chouki Aktouf, Chantal Robach, Guy Mazaré:
Memory testing in a massively parallel machine. 245-252 - Konrad Klöckner:
Advances in object-oriented design. 253 - Peter Loborg, Tore Risch, Martin Sköld, Anders Törne:
Active object oriented databases in control applications. 255-263 - Yoonsook Lee, Songchun Moon:
Heterogeneous schema integration method for multidatabase system. 265-272 - J. Ayre, Derrick Glass, John G. Hughes, I. R. McChesney:
Toward automated support for object-oriented modelling. 273-280 - Markku Oivo
Incremental resources estimation with real-time feedback from measurement. 281-289 - Helmut Rzehak:
Local area networks. 291 - Juan Domingo Sandoval González, F. A. Herrera, Álvaro Suárez Sarmiento, C. Sandoval:
Concurrent ring: Design and evaluation of a new Token Ring LAN. 293-299 - Theodore Antonakopoulos
A distributed bandwidth allocation algorithm for Gbit/s LANs. 301-308 - F. Videira, Augusto Casaca
An ISDN primary rate interface for ethernet access. 309-315 - Rafael Asenjo, Manuel Ujaldon, Emilio L. Zapata:
Parallel WZ factorization on mesh multiprocessors. 319-326 - Massimo Maresca, Pierpaolo Baglietto, A. Giordano:
Image component labeling on reconfigurable processor array. 327-334 - Domingo Giménez, Vicente Hernández, Antonio M. Vidal
Computing the generalized eigenvalues of symmetric positive definite pencils on networks of transputers. 335-342 - N. Scarabotollo:
Session D2: ASIC design. 343 - Béla Fehér:
Efficient synthesis of distributed vector multipliers. 345-350 - D. E. Metafas, Evaggelinos P. Mariatos, Spiridon Nikolaidis
Implementation of Given's Rotation processors for DSP real-time applications. 351-357 - Haralambos C. Karathanasis:
On computing the 2-D discrete cosine transform using rotations. 359-365 - Andrew M. Tyrrell:
Session D3: Data base systems. 367 - Jae Cheol Kwak, Songchun Moon:
Visual query language for object-oriented databases: OQD. 369-376 - Sukhoon Kang, Songchun Moon:
Global query management in heterogeneous distributed database systems. 377-384 - José Ramón González de Mendívil, Carlos F. Alastruey, José Ramón Garitagoitia:
A distributed deadlock detection algorithm for the AND model. 385-392 - András Jávor:
Logic design. 393 - Antonio Lioy
A study of the resetability of synchronous sequential circuits. 395-402 - A. J. W. M. ten Berg, Corrie Huijs, Th. Krol:
Relational algebra as formalism for hardware design. 403-410 - Colin C. Charlton, Paul H. Leng, Mark Rivers:
An object-oriented model of design evolution. 411-418 - Richard McConnell:
Parallelizing compiler techniques. 419-420 - Chu-Sing Yang, Chien-Chih Chang, Jenn-Ming Yang, Tsung-Chuan Huang, K. C. Huang:
Exact and efficient advanced loop interchange. 421-428 - Fermín Sánchez
Resource-constrained pipelining based on loop transformations. 429-436 - Zdzislaw Szczerbinski:
Optimal data dependence chaining in parallel loops. 437-444 - Alessandra Costa, Alessandro De Gloria, Paolo Faraboschi
An asynchronous approach to the RISC design of a micro-controller. 447-454 - Jörg Kottsieper, Klaus Waldschmidt:
Application of the novel associative programmable array-structure multi-match-PLA in synthesis of decomposed finite state machines. 455-465 - Olivier Caron, Vincent Cordonnier, Georges Grimonprez:
OCEAN: A hardware and software tool for design of future smart cards. 467-474 - Kwei-Jay Lin, Kevin B. Kenny:
Implementing and checking timing constraints in real-time programs. 477-484 - Célio Estevan Morón, Hussein Zedan:
On guaranteeing hard real-time tasks. 485-490 - Jinhwan Kim, Heonshik Shin:
Priority-driven concurrency control based on data conflict state in distributed real-time databases. 491-499 - Luigi Carro, César A. M. Marcon, Altamiro A. Suzim:
SHC-SLX: A levelized compiled, event driven interpreted VLSI simulator. 503-509 - Luis Gómez
Timing analysis for DCFL/SDCFL VLSI circuits. 511-518 - Paul E. Dunne
Sequential and parallel strategies for the demand-driven simulation of logic circuits. 519-525 - Stephen Winter:
Application-driven architectures. 527 - Lars Bengtsson, Kenneth Nilsson, Bertil Svensson:
A processor array module for distributed, massively parallel, embedded computing. 529-537 - C. W. Yung, Edward K. N. Yung:
Design of an extended transputer processor farm system. 539-543 - Alessandra Costa, Alessandro De Gloria, Paolo Faraboschi
A parallel architecture for the Color Doppler flow technique in ultrasound imaging. 545-551 - Luis Angel Barragan, Armando Roy:
An empirical study of automatic restructuring of vision programs for simd machines. 553-560 - Cristiana Bolchini
A design methodology for the correct specification of VLSI systems. 563-570 - Johannes Helbig, Rainer Schlör, Werner Damm, Gert Döhmen, Peter Kelb:
VHDL/S - integrating statecharts, timing diagrams, and VHDL. 571-580 - Wolf-Dieter Tiedemann, Stefan Lenk, C. Grobe, Werner Grass:
Introducing structure into behavioural descriptions obtained from timing diagram specifications. 581-588 - Carlos Delgado Kloos, Tomás Pedro de Miguel Moro, Tomás Robles Valladares, Guadalberto Rabay Filho, Andrés Marín López:
VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project. 589-596 - Serafín Olcoz, José Manuel Colom:
Analysis tools applied to VHDL. 597-604 - Krzysztof Sacha:
Real-time specification using Petri nets. 607-614 - Achilles Kameas, Stergios Papadimitriou, Panayiotis E. Pintelas, Georgios Pavlides:
IDFG: An interactive applications specification model with phenomenological properties. 615-623 - Mariam Kamkar, Peter Fritzson, Nahid Shahmehri:
Three approaches to interprocedural dynamic slicing. 625-636 - Matthew J. Gallagher, V. Lakshmi Narasimhan:
A software system for the generation of test data for Ada programs. 637-644 - Kurt P. Judmann:
Issues in distributed systems. 645 - Hidenori Nakazato, Kwei-Jay Lin:
Concurrency control algorithms for real-time systems. 647-654 - V. Lakshmi Narasimhan, S. Price-White:
Analysis and simulation of six bus arbitration protocols. 655-662 - Kyösti Rautiola
Design of TMS320C40 signal processors and programmable logic based prototyping environment of real-time machine vision architectures. 663-668 - Achilles Kameas, Stergios Papadimitriou, Panayiotis E. Pintelas:
Modeling and design of the multimedia subsystem of a distributed authoring environment. 669-678 - Gerd Kock
Neural networks. 679 - Thilo Reski:
Mapping and parallel simulation of synchronous neural networks on multiprocessors. 681-688 - Edoardo Franzi:
Neural accelerator for parallelization of back-propagation algorithm. 689-696 - Eran Tuv, Apostolos Nikolaos Refenes:
Removal of catastrophic noise in hetero-associative training samples. 697-704 - Lech Józwiak:
Algorithms and tools for VLSI design. 705-706 - Xin Yao
An empirical study of genetic operators in genetic algorithms. 707-714 - Károly Tilly, Lászlo Surján, Gyula Román:
Automatic test pattern generation can be solved as a constraint satisfaction problem. 715-722 - Fausto Distante, Paolo Toccaceli:
A behavioral level tool for design and verification of parallel architectures: PADS. 723-730 - G. Ciccarella:
Protocols and performance analysis. 731 - Elena Pagani
Providing circuit service over a high speed deflection network. 733-739 - Rumen Stainov:
Dynamic protocol configuration for multimedia networks. 741-748 - Aristotel Tentov, Aksenti L. Grnarov:
Performance analysis of synchronous multibuffered packet-switching networks. 749-755 - Francisco Tirado:
RT-level synthesis. 757 - S. Baranov, L. Bregman:
Automata decomposition and synthesis with PLAM. 759-766 - Christof Nagel:
Synthesis for testability by synthesis controlling. 767-774 - Rosa M. Badia
Glass: a graph-theoretical approach for global binding. 775-782 - Karl-Erwin Grosspietsch:
Session H1: Fault tolerance. 783 - Andrew M. Tyrrell, Geoffrey F. Carpenter:
The design of time-critical conversations. 785-792 - S Arévalo, Jesús Carretero
A fault-tolerant server on MACH. 793-800 - Bernd Klauer, Klaus Waldschmidt:
Pen-based recognizing of handprinted characters. 803-809 - Katerina Goseva-Popstojanova
N version programming with majority voting decision: Dependability modeling and evaluation. 811-818 - Harald Schummy:
FDT Tools. 819 - Katalin Tarnay, Gyula Csopaki, Maria Törö, M. D. Ta, Zs Boja-Harangozó, J. Miskolczi:
Proconsul, a tool for computer-aided protocol engineering. 821-825 - Maria Törö:
Test strategy for indeterministic protocols. 827-832 - L. P. M. Benders, M. P. J. Stevens:
TL: A system specification system. 835-842 - Gerd Kock
Connectionist model description: A case study. 843-850
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-21 20:16 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: