default search action
5th SIES 2010: Trento, Italy
- IEEE Fifth International Symposium on Industrial Embedded Systems, SIES 2010, University of Trento, Italy, July 7-9, 2010. IEEE 2010, ISBN 978-1-4244-5840-0
System Level
- Sandro Penolazzi, Ingo Sander
, Ahmed Hemani:
Inferring Energy and Performance Cost of RTOS in Priority-Driven Scheduling. 1-8 - Harald Voit, Reinhard Schneider, Dip Goswami, Anuradha Annaswamy, Samarjit Chakraborty
Optimizing Hierarchical Schedules for Improved Control Performance. 9-17 - Michal Sojka
A Comparison of Linux CAN Drivers and their Applications. 18-27 - Christoph Kuznik, Gilles B. Defo, Wolfgang Müller:
Verification of a CAN bus model in SystemC with functional coverage. 28-35
Networks
- Carlo Caione, Davide Brunelli
Compressive sensing optimization over ZigBee networks. 36-44 - Orazio Mirabella, Lucia Lo Bello
An innovative frequency hopping management mechanism for Bluetooth-based industrial networks. 45-50 - Hsin-Chou Chi, Tat-Seng Chang, Chia-Ming Wu:
Design of a Reconfigurable Pipelined Switch for Faulty On-Chip Networks. 51-56
Industrial Designs
- Luca Bochi Saldanha, Robert Hartmann, Christophe Bobda:
Scratch Detector - A FPGA Based System for Scratch Detection in Industrial Picture Development. 57-62 - Alexander Smirnov
Implementation of a bumpless switch in axial magnetic bearings. 63-68 - Koldo Basterretxea, Inés del Campo
A semi-active suspension embedded controller in a FPGA. 69-78 - Kay Klobedanz, Gilles B. Defo, Wolfgang Müller, Timo Kerstan:
Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks. 79-87
Simulation and Methodology
- Mohammad Mostafizur Rahman Mozumdar, Luciano Lavagno, Laura Vanzago, Alberto L. Sangiovanni-Vincentelli
HILAC: A framework for Hardware In the Loop simulation and multi-platform Automatic Code Generation of WSN Applications. 88-97 - Charles André, Frédéric Mallet
VHDL Observers for Clock Constraint Checking. 98-107 - Borzoo Bonakdarpour, Marius Bozga, Mohamad Jaber, Jean Quilbeuf, Joseph Sifakis:
Automated Conflict-free distributed implementation of component-based models. 108-117 - Dominique Gückel, Jörg Brauer, Stefan Kowalewski:
A system for synthesizing abstraction-enabled simulators for binary code verification. 118-127
Real-Time
- Mathieu Jan
Usage of the safety-oriented real-time OASIS approach to build deterministic protection relays. 128-135 - Tommaso Cucinotta
An Exception Based Approach to Timing Constraints Violations in Real-Time and Multimedia Applications. 136-145 - Kristina Kunert, Elisabeth Uhlemann, Magnus Jonsson:
Enhancing Reliability in IEEE 802.11 Based Real-Time Networks through Transport Layer Retransmissions. 146-155
Wireless Networks
- Gianluca Franchino, Giorgio C. Buttazzo, Mauro Marinoni
An Energy-Aware Algorithm for TDMA MAC Protocols in Real-Time Wireless Networks. 156-165 - David Macii
An Energy Saving Criterion for Wireless Sensor Networks with Time Synchronization Requirements. 166-173 - Luca Santinelli, Mangesh Chitnis, Christian Nastasi, Fabio Checconi, Giuseppe Lipari
A Component-Based Architecture for Adaptive Bandwidth Allocation in Wireless Sensor Networks. 174-183
Work-in-Progress
- Khaled Rahmouni, Frédéric Pétrot:
Improving the tests coverage of a medium voltage protection device using system simulation approaches. 184-187 - Chuzo Ninagawa, Tomotaka Sato, Tomohisa Yamada:
Multi-Server Web Industrial Facility Monitoring by Only COTS Browser's Existing Functionality. 188-191 - Maria Isabel de la Fuente, Javier Echanobe
Development of an Embedded System for Visual Servoing in an Industrial Scenario. 192-196 - Xavier Dumas, Frédéric Boniol, Philippe Dhaussy, Eric Bonnafous:
Context Modelling and Partial-Order Reduction: Application to SDL Industrial Embedded Systems. 197-200 - Gunnar Prytz, Jonny Skaalvik:
Redundant and synchronized EtherCAT network. 201-204 - Klaus Schmidt, Ece Guran Schmidt
A Longest-Path Problem for Evaluating the Worst-Case Packet Delay of Switched Ethernet. 205-208 - Ece Guran Schmidt
Performance Evaluation of FlexRay/CAN Networks Interconnected by a Gateway. 209-212 - Swaytha Sasidharan, Fernando Pianegiani, David Macii
A Protocol Performance Comparison in Modular WSNs for Data Center Server Monitoring. 213-216 - Vassiliki Sfyrla, Georgios Tsiligiannis
Compositional Translation of Simulink Models into Synchronous BIP. 217-220 - Kunjesh Shah, Tiberiu Seceleanu
Design and Implementation of a WirelessHART Simulator for Process Control. 221-224 - Sara Real, Hector Posadas, Eugenio Villar:
L2 Cache Modeling based on address modification for Native Co-Simulation in SystemC. 225-228 - Vincent Lefftz, Jean Bertrand, Hugues Cassé, Christophe Clienti, Philippe Coussy, Laurent Maillet-Contoz, Philippe Mercier, Pierre Moreau, Laurence Pierre, Emmanuel Vaumorin:
A Design Flow for Critical Embedded Systems. 229-233 - Julian Viejo
Design and implementation of a suitable core for on-chip long-term verification. 234-237
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-02 18:23 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: