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36th SBCCI 2023: Rio de Janeiro, Brazil
- 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1, 2023. IEEE 2023, ISBN 979-8-3503-1834-0
- Timothy Martin, Charlotte Barnes, Gary William Grewal, Shawki Areibi:
FPGA Placement: Dynamic Decision Making Via Machine Learning. 1-6 - Anaïs Tourissaud, Eric Kerhervé, Nathalie Deltimple, Romain Mathieu:
Study of an Avalanche Compensation Mirror for SiGe High Performance Power Amplifiers Dedicated to 5G Applications. 1-6 - Vanio Rodrigues Filho, Ismael Seidel, Nicole Citadin, Marcio Monteiro, Mateus Grellert
, José Luís Güntzel:
Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FME. 1-6 - Gustavo Comarú
Secure Network Interface for Protecting IO Communication in Many-cores. 1-6 - Willian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. 1-6 - Geancarlo Abich
Power and Performance Costs of Radiation-Hardened ML Inference Models Running on Edge Devices. 1-6 - Rafael da Silva, Mateus Grellert
An Energy-Efficient Interpolation Unit Targeting VVC Encoders with Approximate Adder. 1-5 - Marcello M. Muñoz, Denis Maass, Murilo R. Perleberg
4K UHD@60fps Design For The VVC Affine Motion Estimation Reconstructor. 1-6 - Gabriel T. Gialluca, Gustavo T. Gialluca, Bruno S. Masiero, Eduardo Rodrigues de Lima, Larissa M. Almeida, Fabiano Fruett:
A Wireless Weatherproof Acoustic Sensor System to Detect Anomalies in Substation Power Transformers. 1-6 - Zalfa Jouni
Jitter Noise Impact on Analog Spiking Neural Networks: STDP Limitations. 1-6 - Matthias Kräanzler, André Kaup, Christian Herglotz:
Estimating Software and Hardware Video Decoder Energy Using Software Decoder Profiling. 1-6 - André Beims Bräscher
A New Approach to Video Coding Leveraging Hybrid Coding and Video Frame Interpolation. 1-6 - Anaïs Tourissaud, Eric Kerhervé, Nathalie Deltimple, Steeven Voisin, Romain Mathieu:
A 24.25-30.5GHz Fully Integrated SiGe Phase Shifter/VGA/Power Amplifier in 0.13µm BiCMOS Technology for 5G Beamforming Applications. 1-6 - Cleiton Magano Marques, Leonardo Heitich Brendler, Frédéric Wrobel, Alexandra L. Zimpeck, Walter E. Calienes Bartra
A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures. 1-6 - Felipe A. Kuentzer, Christos Georgakidis, Christos P. Sotiriou, Milos Krstic
Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers. 1-6 - Beatriz E. H. Rezende, João L. J. Brum, Martina C. Rodrigues, Lucas Compassi Severo
Evaluation and Comparison of Offset Compensation Techniques for a Multi-Stage Comparator. 1-6 - Vinicius Zanandrea
New Modified 4:2 Approximate Compressors for Low-Power Applications. 1-6 - Murilo R. Perleberg
An UHD 4K@120fps Hardware for the VVC Prediction Refinement with Optical Flow. 1-6 - Franciele Nornberg, Marcio Bender Machado, Rafael L. Radin, Carlos Galup-Montoro, Márcio C. Schneider:
Design of Oscillator and Charge Pump for the Startup of Ultra-Low-Voltage Energy Harvesters. 1-5 - Állan G. Ferreira, Lucas B. Zilch, Vinícius Navarro, Marcelo Soares Lubaszewski, Tiago R. Balen:
Towards a Machine Learning Based Method for Indirect Test Generation of Mixed-Signal Circuits. 1-6 - Pudi Dhilleswararao, Vamsi Goudu, Srinivas Boppu
Implementation of Image Averaging on DRRA and DiMArch Architectures. 1-6 - Jiovana Sousa Gomes, Rodrigo N. Wuerdig
AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture. 1-6 - Pedro Arthur R. L. Silva, Jeferson F. Chaves, José Augusto Miranda Nacif, Ricardo S. Ferreira, Omar Paranaiba Vilela Neto:
Exploring Nanomagnetic Logic with Bennett Clocking. 1-6 - Rafael S. Ferreira, Luciano Agostini, Cláudio Machado Diniz, Bruno Zatt:
Evaluation of Imprecise Subtractors into Test Zone Search for VVC Encoding. 1-6 - Mateus Castro, Leonardo Sulato de Moraes, Fabio Kelm Pereira, Eduardo Rodrigues de Lima:
A 1.2 V, 80-230 MHz, 1.75 mW Phase Locked Loop N- Integer Clock Synthesizer. 1-5 - Marco P. Stefani, César A. M. Marcon, Felipe G. A. e Silva, Jarbas Silveira:
Memory Controller with Adaptive ECC for Reliable System Operation. 1-6 - Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen
Effect of Unique Table Implementation in the Performance of BDD Packages. 1-6 - Théo Prats Rioufol, Zalfa Jouni
Revisiting the Ultra-Low Power Electronic Neuron Towards a Faithful Biomimetic Behavior. 1-6 - Nicolas Moura, Joaquim Lucena, Eduardo Pereira, Ney Calazans, Luciano Ost, Fernando Moraes, Rafael Garibotti:
Assessment of Lightweight Cryptography Algorithms on ARM Cortex-M Processors. 1-6 - Arthur Mendes Lima, Lucas Giovanni Nardo, Erivelton Geraldo Nepomuceno
Design of an Advanced System-on-Chip Architecture for Chaotic Image Encryption. 1-6 - Carlos Gabriel de Araujo Gewehr
Improving the Efficiency of Cryptography Algorithms on Resource-Constrained Embedded Systems via RISC-V Instruction Set Extensions. 1-6 - Fillipi Mangrich
Energy and Computing Assessment of Video Processing Kernels on CPU and FPGA platforms. 1-6 - C. Acuña, C. Flores, Jimmy Tarrillo
FPGA-Based Brain-Computer Interface System for Real-Time Eye State Classification. 1-6 - Stefan T. Couperus Leal, Michael Canesche, Omar P. Vilela Neto, Ricardo S. Ferreira, José A. M. Nacif:
A Non-Blocking Multistage Interconnection using Regular Clock Schemes for QCA Circuits. 1-6 - Bianca Silveira, Daniel Palomino, Cláudio Machado Diniz, Guilherme Corrêa:
A Hardware Design for the Multi-Transform Module of the Versatile Video Coding Standard. 1-6 - Jose Mendoza-Peñaloza, Daniel M. Muñoz:
Hardware Implementation of a Sliding Detection Algorithm for Robotic Hands Using Force Sensors. 1-6 - Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen
ATMR design by construction based on two-level ALS. 1-6 - M. P. Braga de Lima, Fernando A. P. Barúqui, Carlos Fernando Teodósio Soares:
Voltage Regulator with Ellipsoidal Transistors. 1-4
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