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32nd ISMVL 2002: Boston, Massachusetts, USA
- 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA. IEEE Computer Society 2002, ISBN 0-7695-1462-6
Invited Talk
- Sergiu Rudeanu:
Equations in the Algebra of Logic. 2-9
Algebra I
- Hajime Machida, Masahiro Miyakawa, Ivo G. Rosenberg:
Some Results on the Centralizers of Monoids in Clone Theory. 10-16 - Boris A. Romov:
Partial Hyperclones on a Finite Set. 17-22 - Michiro Kondo:
On the Structures of Weak Interlaced Bilattice. 23-27
Logical Design I
- Claudio Moraga:
Improving the Characterization of p-Valued Threshold Functions. 28-34 - Elena Dubrova, Petra Färm:
A Conjunctive Canonical Expansion of Multiple-Valued Functions. 35-38 - Denis V. Popel, Anita Dani
:
Sierpinski Gaskets for Logic Functions Representation. 39-45 - Noboru Takagi, Kyoichi Nakashima:
Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals. 46-53
Circuits I
- Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi:
Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. 54-60 - Takao Waho, Shin-ya Kobayashi, Koji Matsuura:
An Impact of Introducing Multi-Level Signals to a Bandpass Cascaded Delta-Sigma Modulator. 61-66 - Yongjian Brandon Guo, K. Wayne Current:
Voltage Comparator Circuits for Multiple-Valued CMOS Logic. 67-75
Logical Design II
- Dragan Jankovic
Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic Functions. 76-82 - K. J. Adams, J. McGregor:
Comparison of Different Features of Quaternary Reed-Muller Canonical Forms and Some New Statistical Results. 83-88 - Boris Polianskikh, Zeljko Zilic:
Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection. 89-95 - Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi:
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. 96-103
Invited Talk
- Vincenzo Marra, Daniele Mundici:
Consequence and Complexity in Infinite-Valued Logic: A Survey. 104-115
Spectral Techniques
- Radomir S. Stankovic, Jaakko Astola:
Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams. 116-122 - Mitchell A. Thornton
Chrestenson Spectrum Computation Using Cayley Color Graphs. 123-129 - Zeljko Zilic, Katarzyna Radecka:
The Role of Super-Fast Transforms in Speeding Up Quantum Computations. 129-135 - Bogdan J. Falkowski, Beata T. Olejnicka:
Multiple-Valued and Spectral Approach to Lossless Compression of Binary, Gray Scale and Color Biomedical Images. 136-143
Circuits II
- Elena N. Zaitseva, Vitaly G. Levashenko:
Design of Dynamic Reliability Indices. 144-148 - Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui:
PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits. 149-155 - Yinshui Xia, Xunwei Wu, Penjung Wang:
Design of Ternary Schmitt Triggers Based on Its Sequential Characteristics. 156-160 - Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama:
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. 161-167
Invited Talk
- Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks. 168-179
Algebra II
- Hiroaki Kikuchi, Noboru Takagi:
de Morgan Bisemilattice of Fuzzy Truth Value. 180-184 - Tomoko Ninomiya, Masao Mukaidono:
Independence of Each Axiom in a Set of Axioms and Complete Sets of Axioms of Boolean Algebra. 185-191 - Ivo G. Rosenberg, Dan A. Simovici, Szymon Jaroszewicz
On Functions Defined on Free Boolean Algebras. 192-201
Logical Design III
- Svetlana N. Yanushkevich
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based Model. 202-208 - Anna M. Tomaszewska, Svetlana N. Yanushkevich
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model. 209-215 - Ilia Polian, Piet Engelke, Bernd Becker:
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. 216-223
Invited Talk
- Naofumi Takagi:
Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms. 224-237
Decision Diagrams
- Masahiro Miyakawa, Nobuyuki Otsu, Ivo G. Rosenberg:
Variable Selection Heuristics and Optimum Decision Trees - An Experimental Study. 238-244 - D. Michael Miller, Rolf Drechsler:
On the Construction of Multiple-Valued Decision Diagrams. 245-253 - Rolf Drechsler:
Evaluation of Static Variable Ordering Heuristics for MDD Construction. 254-260 - Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura:
Representations of Logic Functions Using QRMDDs. 261-269
Circuits III
- Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama:
Fully Source-Coupled Logic Based Multiple-Valued VLSI. 270-275 - Sung Il Han, Seung-Yong Park, Hyeon Kyeong Seong, Heung-Soo Kim:
A Current-Mode Folding/Interpolating CMOS Analog to Quaternary Converter Using Binary to Quaternary Encoding Block. 276-281 - Motoi Inaba, Koichi Tanno, Okihiko Ishizuka:
Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. 282-288
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