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28th ISMVL 1998: Fukuoka, Japan
- 28th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1998, Fukuoka, Japan, May 27-29, 1998, Proceedings. IEEE Computer Society 1998, ISBN 0-8186-8371-6
Invited Address
- Takashi Okuda:
Advanced Circuit Technology to Realize Post Giga-bit DRAM. 2-5
Devices
- Toshio Baba, Tetsuya Uemura:
Development of InGaAs-Based Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits. 7-12 - Toshihiro Itoh, Takao Waho, Koichi Maezawa, Masafumi Yamamoto:
Ultrafast Ternary Quantizer using Resonant Tunneling Devices. 13-18 - Mititada Morisue, Jun Endo, Toshimitu Morooka, Nobuhiro Shimizu, Masahiro Sakamoto:
A Josephson Ternary Memory Circuit. 19-24
Cellular Array and Fault Tolerance
- I. Takanami:
A Note on Realizing Multiple-Valued Logic Functions using Akers' Cells - Cell Sizes and Path Lengths. 26-31 - Ning Song, Marek A. Perkowski:
Minimization of Exclusive Sums of Multi-Valued Complex Terms for Logic Cell Arrays. 32-37 - Yasunori Nagata, D. Michael Miller, Masao Mukaidono:
Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs. 38-44
Decision Diagrams
- Hafiz Md. Hasan Babu, Tsutomu Sasao:
Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams. 45-51 - D. Michael Miller, Rolf Drechsler:
Implementing a Multiple-Valued Decision Diagram Package. 52-57 - Luca Macchiarulo, Pierluigi Civera:
Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis. 58-64
Algebra 1
- Hwan Mook Chung, Su Young Pi, Siegfried Rey:
The MacLaurin's and Taylor's Series Expansions of the Symbolic Multiple Valued Logic Functions. 65-70 - Noboru Takagi, Akimitsu Hon-nami, Kyoichi Nakashima:
A Characterization of r-Valued Functions Monotonic in an Order Based on Regularity. 71-76 - Renren Liu:
Some Results on the Decision for Sheffer Functions in Partial K-Valued Logic(II). 77-82
Logic Design 1
- Jon T. Butler, Tsutomu Sasao:
On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels. 83-88 - Claudio Moraga, Wenjun Wang:
Evolutionary Methods in the Design of Quaternery Digital Circuits. 89-94 - Per Lindgren, Rolf Drechsler, Bernd Becker:
Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions. 95-101
Logic
- Robert J. Bignall, Matthew Spinks:
Multiple-Valued Logics for Theorem-Proving in First Order Logic with Equality. 102-107 - Matthias Baaz, Richard Zach
:
Compact Propositional Gödel Logics. 108-113 - Seiki Akama, Jair Minoro Abe
Many-Valued and Annotated Modal Logics. 114-120
Invited Address
- Zvonko G. Vranesic:
The FPGA Challenge. 121-127
VLSI Circuits 1
- Jing Shen, Koichi Tanno, Okihiko Ishizuka, Zheng Tang:
Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits. 128-133 - Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama:
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. 134-139 - Takafumi Aoki, Tatsuo Higuchi:
Set-Valued Logic Circuits for Next Generation VLSI Architectures. 140-147 - Yasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi:
Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences. 148-154
Applications of Multiple-Valued Logic
- Yutaka Hata, Makoto Ishikawa, Naotake Kamiura:
Image Segmentation Based on Kleene Algebra. 155-160 - Alioune Ngom, Corina Reischer, Dan A. Simovici, Ivan Stojmenovic:
Learning with Permutably Homogenous Multiple-Valued Multiple-Threshold Perceptrons. 161-166 - Craig M. Files, Marek A. Perkowski:
An Error Reducing Approach to Machine Learning using Multi-Valued Functional Decomposition. 167-172 - Craig M. Files, Marek A. Perkowski:
Multi-Valued Functional Decomposition as a Machine Learning Method. 173-179
Logic Design 2
- Bogdan J. Falkowski:
Fast Multi-Polarity Complex Hadamard Transform for Logic Functions. 180-185 - Radomir S. Stankovic, Dragan Jankovic, Claudio Moraga:
Reed-Muller-Fourier versus Galois Field Representations of Four-Valued Logic Functions. 186-191 - Lawrence J. Thaden:
Constructing an MVL Patterned after Boolean Logic using a Practical Approach. 192-200
Genetic Algorithms in MVL
- Yoshinori Yamamoto:
A Synthesis Method of the Approximate Reasoning Engine by means of Genetic Algorithm. 201-208 - Alioune Ngom, Ivan Stojmenovic, Zoran Obradovic:
Minimization of Multivalued Multithreshold Perceptrons using Genetic Algorithms. 209-214 - Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker:
Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. 215-221
Invited Address
- P. Glenn Gulak:
A Review of Multiple-Valued Memory Technology. 222-231
Minimization
- Takahiro Hozumi, Osamu Kakusho, Yutaka Hata:
On Low Cost Realization of Multiple-Valued Logic Functions. 233-238 - Blair Fraser, Gerhard W. Dueck:
Multiple-Valued Logic Minimization using Universal Literals and Cost Tables. 239-244 - Mostafa I. H. Abd-El-Barr, Muhammad M. Abd-El-Barr:
A Frontier Algorithm for Optimization of Multiple-Valued Logic Functions. 245-249
Algebra 2
- Grant Pogosyan, Takashi Nakamura:
e-Bases of Triadic Logic Operations. 251-256 - V. Cheushev, Vlad P. Shmerko, Dan A. Simovici, Svetlana N. Yanushkevich
Functional Entropy and Decision Trees. 257-263
VLSI Circuits 2
- Ali Sheikholeslami, R. Yoshimura, P. Glenn Gulak:
Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic. 264-269 - Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama:
Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. 270-275 - Shugang Wei, Kensuke Shimizu:
Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits. 276-281 - Katsuhiko Shimabukuro, Chotei Zukeran:
Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic Circuits. 282-288
Theory of Fuzzy Logic
- Tomoyuki Araki, Hisayuki Tatsumi, Masao Mukaidono, F. Yamamoto:
Minimization of Incompletely Specified Regular Ternary Logic Functions and its Application to Fuzzy Switching Functions. 289-296 - Hisayuki Tatsumi, Tomoyuki Araki, Masao Mukaidono, Shinji Tokumasu:
Upper and Lower Bounds on the Number of Fuzzy/c Switching Functions. 297-303 - Helmut Thiele:
On Closure Operators in Fuzzy Deductive Systems and Fuzzy Algebras. 304-309 - Yukari Yamauchi, Masao Mukaidono:
A Study on Operations in Interval and Paired Probabilities. 310-316
Invited Address
- Tadashi Shibata:
Functional-Device-Based VLSI for Intelligent Electronic Systems. 317-325
Invited Address
- Ivo G. Rosenberg:
Multiple-Valued Hyperstructures. 326-334
Invited Address
- Takeshi Yamakawa:
A Novel Nonlinear Synapse Neuron Model Guaranteeing a Global Minimum - Wavelet Neuron. 335-337
Applications of Fuzzy Logic
- Cengiz Kahraman, Ethem Tolga:
Data Envelopment Analysis using Fuzzy Concept. 338-343 - Fumio Wakui, Masato Hirano:
A Proposal and an Application of a Career-Mode Membership Function. 344-349 - Masataka Tokumaru, Kazumi Yamashita, Noriaki Muranaka, Shigeru Imanishi:
Membership Functions in Automatic Harmonization System. 350-355 - Naotake Kamiura, Yutaka Hata, Kazuharu Yamato:
On Concurrent Tests of Fuzzy Controllers. 356-362
Clone Theory
- Ferdinand Börner, Lucien Haddad:
Generating Sets for Clones and Partial Clones. 363-368 - Jean Fugère, Lucien Haddad:
On Partial Clones Containing All Idempotent Partial Operations. 369-373 - Hajime Machida:
Some Continuous Maps on the Space of Clones in Multiple-Valued Logic. 374-379 - Akihiro Nozaki, Vaktang Lashkia:
A Finite Basis of the Set of All Monotone Partial Functions Defined over a Finite Poset. 380-382
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