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HPEC 2014: Waltham, MA, USA
- IEEE High Performance Extreme Computing Conference, HPEC 2014, Waltham, MA, USA, September 9-11, 2014. IEEE 2014, ISBN 978-1-4799-6233-4
- Oren Segal, Nasibeh Nasiri, Martin Margala
, Wim Vanderbauwhede:
High level programming of FPGAs for HPC and data centric applications. 1-3 - Wei Dai
Accelerating NTRU based homomorphic encryption using GPUs. 1-6 - Raymond R. Hoare, Denis Smetana:
Accelerating SAR processing on COTS FPGA hardware using C-to-gates design tools. 1-6 - Andrew Milluzzi, Justin Richardson, Alan D. George, Herman Lam:
A multi-tiered optimization framework for heterogeneous computing. 1-6 - Daniel Kimball, Elizabeth Michel, Paul Keltcher, Michael M. Wolf:
Quantifying the effect of matrix structure on multithreaded performance of the SpMV kernel. 1-6 - Robert F. Lucas, Gene Wagenbreth:
Multifrontal computations on accelerators. 1-6 - Berkin Akin, James C. Hoe, Franz Franchetti:
HAMLeT: Hardware accelerated memory layout transform within 3D-stacked DRAM. 1-6 - Raphael Landaverde, Martin C. Herbordt:
GPU optimizations for a production molecular docking code. 1-6 - Saurabh Hukerikar, Keita Teranishi, Pedro C. Diniz, Robert F. Lucas:
An evaluation of lazy fault detection based on Adaptive Redundant Multithreading. 1-6 - Gregory Emmett Coxson, Connie R. Hill, Jon Carmelo Russo:
Adiabatic quantum computing for finding low-peak-sidelobe codes. 1-6 - Cetin Savkli, Ryan Carr, Matthew Chapman, Brant Chee
Socrates - A System For Scalable Graph Analytics. 1-6 - Sophia Yakoubov
A survey of cryptographic approaches to securing big-data analytics in the cloud. 1-6 - Shijie Zhou, Shreyas G. Singapura, Viktor K. Prasanna:
High-performance packet classification on GPU. 1-6 - Adam McLaughlin, E. Jason Riedy
Optimizing energy consumption and parallel performance for static and dynamic betweenness centrality using GPUs. 1-6 - Alok Gautam Kumbhare, Marc Frîncu, Cauligi S. Raghavendra, Viktor K. Prasanna:
Efficient extraction of high centrality vertices in distributed graphs. 1-7 - Timothy J. Dysart, Jay B. Brockman, Stephen Jones, Fred Bacon:
Embedded real-time HD video deblurring. 1-6 - Fan Zhang, Yang Gao, Jason D. Bakos:
Lucas-Kanade Optical Flow estimation on the TI C66x digital signal processor. 1-6 - Muthu Manikandan Baskaran, Benoît Meister, Richard Lethin:
Low-overhead load-balanced scheduling for sparse tensor computations. 1-6 - Jordi Ros-Giralt, Alan Commike, R. Rotsted, P. Clancy, A. Johnson, Richard A. Lethin:
Lockless hash tables with low false negatives. 1-6 - Peter Holvenstot, Diana Prieto
GPGPU parallelization of self-calibrating agent-based influenza outbreak simulation. 1-6 - Charles Gala, Raj Acharya, Bruce Einfalt:
Utilizing Graphics Processing Units for rapid facial recognition using video input. 1-6 - Yang Gao, Fan Zhang, Jason D. Bakos:
Sparse matrix-vector multiply on the Keystone II Digital Signal Processor. 1-6 - Xiaoxiao Liu
A heterogeneous computing system with memristor-based neuromorphic accelerators. 1-6 - Rob F. Van der Wijngaart, Timothy G. Mattson:
The Parallel Research Kernels. 1-6 - Tung Thanh Hoang, Amirali Shambayati, Calvin Deutschbein
Performance and energy limits of a processor-integrated FFT accelerator. 1-6 - Fazle Sadi, Berkin Akin, Doru-Thom Popovici, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory. 1-6 - Michael M. Wolf, Benjamin A. Miller:
Sparse matrix partitioning for parallel eigenanalysis of large static and dynamic graphs. 1-6 - Jin Zhao, Bingqian Xie, Xinming Huang:
Real-time lane departure and front collision warning system on an FPGA. 1-5 - Torben Kling Petersen, John Fragalla:
Enterprise HPC storage systems. 1-6 - James Kingsley, Zhilu Chen, Jeffrey Bibeau, Luis Vidali
A GPU accelerated virtual scanning confocal microscope. 1-6 - Raphael Landaverde, Tiansheng Zhang
An investigation of Unified Memory Access performance in CUDA. 1-6 - Robert W. Techentin, Daniel Foti, Sinan Al-Saffar, Peter Li, Erik S. Daniel, Barry K. Gilbert, David R. Holmes:
Characterization of semi-synthetic dataset for big-data semantic analysis. 1-6 - David Bruce Cousins, John Golusky, Kurt Rohloff
An FPGA co-processor implementation of Homomorphic Encryption. 1-6 - Michel A. Kinsy, Srinivas Devadas:
Low-overhead hard real-time aware interconnect network router. 1-6 - Sanmukh R. Kuppannagari
Energy performance of FPGAs on PERFECT suite kernels. 1-6 - Ren Chen, Viktor K. Prasanna:
Energy optimizations for FPGA-based 2-D FFT architecture. 1-6 - Scott M. Sawyer, B. David O'Gwynn:
Evaluating accumulo performance for a scalable cyber data processing pipeline. 1-6 - Charith Wickramaarachchi, Marc Frîncu, Patrick Small, Viktor K. Prasanna:
Fast parallel algorithm for unfolding of communities in large graphs. 1-6 - Vladimir Ufimtsev, Sanjukta Bhowmick, Sivasankaran Rajamanickam:
Building blocks for graph based network analysis. 1-6 - Jeremy Kepner, William Arcand, David Bestor, Bill Bergeron, Chansup Byun, Vijay Gadepally, Matthew Hubbell, Peter Michaleas, Julie Mullen, Andrew Prout, Albert Reuther, Antonio Rosa, Charles Yee:
Achieving 100, 000, 000 database inserts per second using Accumulo and D4M. 1-6 - Anamaria Vizitiu, Lucian Mihai Itu, Cosmin Nita, Constantin Suciu:
Optimized three-dimensional stencil computation on Fermi and Kepler GPUs. 1-6 - James Chacko, Cem Sahin, Danh H. Nguyen
FPGA-based latency-insensitive OFDM pipeline for wireless research. 1-6 - Jiayi Sheng, Ben Humphries, Hansen Zhang, Martin C. Herbordt:
Design of 3D FFTs with FPGA clusters. 1-6 - Yun Rock Qu, Viktor K. Prasanna:
Scalable and dynamically updatable lookup engine for decision-trees on FPGA. 1-6 - Shuai Che, Bradford M. Beckmann, Steven K. Reinhardt:
BelRed: Constructing GPGPU graph applications with software building blocks. 1-6 - Yusong Hu, Viktor K. Prasanna:
Energy- and area-efficient parameterized lifting-based 2-D DWT architecture on FPGA. 1-6 - David Ediger, D. Scott Appling, Erica Briscoe, Robert McColl, Jason Poovey:
Real-time streaming intelligence: Integrating graph and NLP analytics. 1-6 - Stephanie Dodson, Darrell O. Ricke, Jeremy Kepner:
Genetic sequence matching using D4M big data approaches. 1-6 - Ariel Hamlin, Jonathan Herzog:
A test-suite generator for database systems. 1-6 - Mohammed K. Ali Shatnawi, Hussein Ali Shatnawi:
A performance model of fast 2D-DCT parallel JPEG encoding using CUDA GPU and SMP-architecture. 1-6 - Massimiliano Fatica, Everett H. Phillips:
Synthetic aperture radar imaging on a CUDA-enabled mobile platform. 1-5 - Dmitry Mishin, Kieran Brantner-Magee, Ferenc Czako, Alexander S. Szalay:
Real time change point detection by incremental PCA in large scale sensor data. 1-6 - Mahsa Bayati, Jaydeep P. Bardhan, David M. King, Miriam Leeser
Accelerating protein coordinate conversion using GPUs. 1-6 - Jeremy Kepner, Vijay Gadepally, Peter Michaleas, Nabil Schear, Mayank Varia, Arkady Yerukhimovich, Robert K. Cunningham:
Computing on masked data: a high performance method for improving big data veracity. 1-6 - Andrea Sanny, Yi-Hua E. Yang, Viktor K. Prasanna:
Energy-efficient histogram equalization on FPGA. 1-6 - Geoffrey Phi C. Tran, Dong-In Kang, Stephen P. Crago:
Dynamic runtime optimizations for systems of heterogeneous architectures. 1-6 - James A. Ross, David A. Richie, Song Jun Park, Dale R. Shires, Lori L. Pollock:
A case study of OpenCL on an Android mobile GPU. 1-6 - Vijay Gadepally, Jeremy Kepner:
Big data dimensional analysis. 1-6 - Thomas M. Benson:
A system-level optimization framework for high-performance networking. 1-6 - Vivek Venugopalan
Evaluating latency and throughput bound acceleration of FPGAs and GPUs for adaptive optics algorithms. 1-6 - Michel A. Kinsy, Srinivas Devadas:
Algorithms for scheduling task-based applications onto heterogeneous many-core architectures. 1-6 - Barath Ramesh, Asheesh Bhardwaj, Justin Richardson, Alan D. George
Optimization and evaluation of image- and signal-processing kernels on the TI C6678 multi-core DSP. 1-6 - Shuai Che:
GasCL: A vertex-centric graph model for GPUs. 1-6 - Aysegul Dundar, Jonghoon Jin, Vinayak Gokhale, Berin Martini, Eugenio Culurciello:
Memory access optimized routing scheme for deep networks on a mobile coprocessor. 1-6 - James R. Ezick, Jonathan Springer, Tom Henretty, Chanseok Oh:
Extreme SAT-based Constraint solving with R-Solve. 1-6
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