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18th FMCAD 2018: Austin, TX, USA
- Nikolaj S. Bjørner, Arie Gurfinkel:
2018 Formal Methods in Computer Aided Design, FMCAD 2018, Austin, TX, USA, October 30 - November 2, 2018. IEEE 2018, ISBN 978-0-9835678-8-2 - Bernhard K. Aichernig
, Roderick Bloem
Automata Learning for Symbolic Execution. 1-9 - Adrian Rebola-Pardo, Luís Cruz-Filipe:
Complete and Efficient DRAT Proof Checking. 1-9 - John Backes, Pauline Bolignano, Byron Cook, Catherine Dodge, Andrew Gacek, Kasper Søe Luckow, Neha Rungta, Oksana Tkachuk, Carsten Varming:
Semantic-based Automated Reasoning for AWS Access Policies using SMT. 1-9 - Dejan Jovanovic, Andrew Reynolds:
The FMCAD 2018 Graduate Student Forum. 1 - Parosh Aziz Abdulla, Mohamed Faouzi Atig, Yu-Fang Chen, Bui Phi Diep, Lukás Holík
Trau: SMT solver for string constraints. 1-5 - Alexander Ivrii, Ziv Nevo, Jason Baumgartner:
k-FAIR = k-LIVENESS + FAIR Revisiting SAT-based Liveness Algorithms. 1-5 - Sourav Anand, Nadia Polikarpova:
Automatic Synchronization for GPU Kernels. 1-9 - Supratik Chakraborty
Functional Synthesis via Input-Output Separation. 1-9 - Julien Brunel, David Chemouil, Jeanne Tawa:
Analyzing the Fundamental Liveness Property of the Chord Protocol. 1-9 - Bjørnar Luteberget
Design-Time Railway Capacity Verification using SAT modulo Discrete Event Simulation. 1-9 - Roderick Bloem
Expansion-Based QBF Solving Without Recursion. 1-10 - Pavel Cadek, Clemens Danninger, Moritz Sinn, Florian Zuleger
Using Loop Bound Analysis For Invariant Generation. 1-9 - Eugene Goldberg:
Complete Test Sets And Their Approximations. 1-9 - Roberto Cavada, Alessandro Cimatti, Sergio Mover, Mirko Sessa
Analysis of Relay Interlocking Systems via SMT-based Model Checking of Switched Multi-Domain Kirchhoff Networks. 1-9 - Oded Padon, Jochen Hoenicke
Temporal Prophecy for Proving Temporal Properties of Infinite-State Systems. 1-11 - Viktor Malík
Template-Based Verification of Heap-Manipulating Programs. 1-9 - Oded Padon:
Deductive Verification of Distributed Protocols in First-Order Logic. 1 - Grigory Fedyukovich
Solving Constrained Horn Clauses Using Syntax and Data. 1-9 - Hossein Hojjat, Philipp Rümmer:
The ELDARICA Horn Solver. 1-7 - Cristian Mattarei, Makai Mann, Clark W. Barrett, Ross G. Daly, Dillon Huff, Pat Hanrahan:
CoSA: Integrated Verification for Agile Hardware Design. 1-5 - Hongce Zhang
ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification. 1-10 - Daniel Neider, Ivan Gavran:
Learning Linear Temporal Properties. 1-10 - Nina Narodytska:
Formal Verification of Deep Neural Networks. 1 - Vikas Rao, Utkarsh Gupta, Irina Ilioaea, Arpitha Srinath, Priyank Kalla, Florian Enescu
Post-Verification Debugging and Rectification of Finite Field Arithmetic Circuits using Computer Algebra Techniques. 1-9 - Heiko Becker, Nikita Zyuzin, Raphaël Monat, Eva Darulova
A Verified Certificate Checker for Finite-Precision Error Bounds in Coq and HOL4. 1-10 - Thomas Pani, Georg Weissenbacher
Rely-Guarantee Reasoning for Automated Bound Analysis of Lock-Free Algorithms. 1-9 - Hernán Ponce de León, Florian Furbach, Keijo Heljanko
BMC with Memory Models as Modules. 1-9 - Alberto Griggio
Certifying Proofs for LTL Model Checking. 1-9 - Peter Backeman, Philipp Rümmer, Aleksandar Zeljic:
Bit-Vector Interpolation and Quantifier Elimination by Lazy Reduction. 1-10
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