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14th FCCM 2006: Napa, CA, USA
- 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings. IEEE Computer Society 2006, ISBN 0-7695-2661-6
Session 1: Supercomputer Applications
- Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson:
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer. 3-12 - Volodymyr V. Kindratenko
, David Pointer:
A case study in porting a production scientific supercomputing application to a reconfigurable computer. 13-22 - Ronald Scrofano, Maya B. Gokhale, Frans Trouw, Viktor K. Prasanna:
Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers. 23-34
Session 2: Methodology and Tools
- Chun Hok Ho, Philip Heng Wai Leong
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. 35-44 - David J. Lau, Orion Pritchard, Philippe Molson:
Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions. 45-56
Session 3: Data Generation and Processing
- David B. Thomas, Wayne Luk:
Efficient Hardware Generation of Random Variates with Arbitrary Distributions. 57-66 - Zachary K. Baker, Viktor K. Prasanna:
An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems. 67-75 - Haiqian Yu, Miriam Leeser
Automatic Sliding Window Operation Optimization for FPGA-Based. 76-88
Session 4: Hybrid Systems
- Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David Andrews
Enabling a Uniform Programming Model Across the Software/Hardware Boundary. 89-98 - Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling:
A Type Architecture for Hybrid Micro-Parallel Computers. 99-110
Session 5: Multi-processor/Threaded System
- Arun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Régis Pomès, Paul Chow:
A Scalable FPGA-based Multiprocessor. 111-120 - Charles L. Cathey, Jason D. Bakos, Duncan A. Buell
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism. 121-130 - Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown:
A Multithreaded Soft Processor for SoPC Area Reduction. 131-142
Session 6: Graph Algorithms
- Michael DeLorimier, Nachiket Kapre
GraphStep: A System Architecture for Sparse-Graph Algorithms. 143-151 - Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan:
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths. 152-164
Session 7: Power and Energy Optimization
- Alex K. Jones
A Field Programmable RFID Tag and Associated Design Flow. 165-174 - Robert G. Dimond, Oskar Mencer, Wayne Luk:
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA. 175-184 - Matthew French, Li Wang, Michael J. Wirthlin:
Power Visualization, Analysis, and Optimization Tools for FPGAs. 185-194
Session 8: Network Technology
- Michael Attig, Gordon J. Brebner
Systematic Characterization of Programmable Packet Processing Pipelines. 195-204 - Nachiket Kapre
Packet Switched vs. Time Multiplexed FPGA Overlay Networks. 205-216
Session 9: Biomedical and Cryptographic Applications
- Martin C. Herbordt, Josh Model, Yongfeng Gu, Bharat Sukhwani, Tom Van Court:
Single Pass, BLAST-Like, Approximate String Matching on FPGAs. 217-226 - Kevin Whitton, Xiaobo Sharon Hu
An FPGA Solution for Radiation Dose Calculation. 227-236 - Andrey Bogdanov, M. C. Mertens, Christof Paar, Jan Pelzl, Andy Rupp
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2). 237-248
Session 10: Arithmetic
- Xiaojun Wang, Sherman Braganza, Miriam Leeser
Advanced Components in the Variable Precision Floating-Point Library. 249-258 - Robert Strzodka, Dominik Göddeke
Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components. 259-270
Posters
- Evgeny Fiksman, Yitzhak Birk
ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills. 271-272 - Shannon Koh, Oliver Diessel
COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs. 273-274 - Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. 275-276 - Gang Wang, Wenrui Gong, Ryan Kastner
Defect-Tolerant Nanocomputing Using Bloom Filters. 277-278 - Reid B. Porter, Jan R. Frigo, Maya B. Gokhale, Christophe Wolinski, François Charot, Charles Wagner:
A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing. 279-280 - Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann
VPN Acceleration Using Reconfigurable System-On-Chip Technology. 281-282 - Chuan He, Guan Qin, Mi Lu, Wei Zhao
An Optimized Finite Difference Computing Engine on FPGAs. 283-284 - Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi:
Highly Efficient String Matching Circuit for IDS with FPGA. 285-286 - Rafael A. Arce-Nazario
Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures. 287-288 - K. N. Vikram, Vinita Vasudevan
Scheduling divisible loads on partially reconfigurable hardware. 289-290 - Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata
General Architecture for Hardware Implementation of Genetic Algorithm. 291-292 - Yousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos:
Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs. 293-294 - Arpith C. Jacob, Brandon Harris, Jeremy Buhler
Scalable Softcore Vector Processor for Biosequence Applications. 295-296 - Oliver Pell, Wayne Luk:
Generating Parametrised Hardware Libraries from Higher-Order Descriptions. 297-298 - Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones
Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). 299-300 - Gerhard Lienhart, Guillermo Marcus Martinez
Rapid Design of Special-Purpose Pipeline Processors with FPGAs and its Application to Computational Fluid Dynamics. 301-302 - Michael R. Bodnar, John R. Humphrey, Petersen F. Curt, James P. Durbano, Dennis W. Prather:
Floating-Point Accumulation Circuit for Matrix Applications. 303-304 - Tom Van Court, Martin C. Herbordt:
Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid Computations. 305-306 - Kyprianos Papademetriou
A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems. 307-308 - Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones
A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. 309-310 - Sandeep S. Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler:
COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking. 311-312 - Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann:
FPGAs, GPUs and the PS2 - A Single Programming Methodology. 313-314 - Yongfeng Gu, Tom Van Court, Martin C. Herbordt:
Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report. 315-316 - Charlie Ross, A. P. Wim Böhm:
A Co-Verification Tool for a High Level Language Compiler for FPGAs. 317-318 - Dionissios Efstathiou, Konstantinos Kazakos, Apostolos Dollas:
Parrotfish: Task Distribution in a Low Cost Autonomous ad hoc Sensor Network through Dynamic Runtime Reconfiguration. 319-320 - John Maher, Brian McGinley
Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices. 321-322 - Heather Quinn, Debayan Bhaduri, Christof Teuscher, Paul S. Graham, Maya B. Gokhale:
The STAR-C Truth: Analyzing Reconfigurable Supercomputing Reliability. 323-324 - Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas
Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs. 325-326 - Shobana Padmanabhan, Moshe Looks, Dan Legorreta, Young H. Cho, John W. Lockwood:
Hierarchical Clustering using Reconfigurable Devices. 327-328 - Simin Dai, Elaheh Bozorgzadeh:
CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures. 329-330 - Allen Michalski, Duncan A. Buell
A Scalable Architecture for RSA Cryptography on Large FPGAs. 331-332 - Kendall Ananyi, Daler N. Rakhmatov:
Design of a Reconfigurable Processor for NIST Prime Field ECC. 333-334 - Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman:
Switch Box Architectures for Three-Dimensional FPGAs. 335-336 - James Moscola, Young H. Cho, John W. Lockwood:
A Scalable Hybrid Regular Expression Pattern Matcher. 337-338 - Cao Liang, Jing Ma, Xinming Huang:
Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms. 339-340 - Jia Ming Mar, Alessandro Bissacco, Stefano Soatto, Soheil Ghiasi:
High Performance Feature Detection on a Reconfigurable Co-Processor. 341-342 - Michael J. Wirthlin, Welson Sun:
DSynth: A Pipeline Synthesis Environment for FPGAs. 343-344 - Nikolaos Bellas
Template-Based Generation of Streaming Accelators from a High Level Presentation. 345-346 - Brad Matthews, Itamar Elhanany:
Scalable Hardware Architecture for Real-Time Dynamic Programming Applications. 347-348 - K. Scott Hemmert, Keith D. Underwood:
Open Source High Performance Floating-Point Modules. 349-350 - John A. Williams
A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer. 351-352
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