default search action
16th ASYNC 2010: Grenoble, France
- 16th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2010, Grenoble, France, 3-6 May 2010. IEEE Computer Society 2010, ISBN 978-0-7695-4032-0
Logic and Physical Synthesis
- Ad M. G. Peeters, Frank te Beest, Mark de Wit, Willem C. Mallon:
Click Elements: An Implementation Style for Data-Driven Compilation. 3-14 - William B. Toms, David A. Edwards:
M-of-N Code Decomposition for Indicating Combinational Logic. 15-25 - Santosh N. Varanasi, Kenneth S. Stevens, Graham M. Birtwistle:
Concurrency Reduction of Untimed Latch Protocols - Theory and Practice. 26-37
Low-Power and Harvesting
- Omer Can Akgun
, Joachim Neves Rodrigues, Jens Sparsø
Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study. 41-51 - Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar:
Static Power Reduction Techniques for Asynchronous Circuits. 52-61 - Jean-Frédéric Christmann, Edith Beigné
Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems. 62-71
Synchronisers
- William J. Dally, Stephen G. Tell:
The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer. 75-84 - Jun Zhou, Maryam Ashouei, David Kinniment, Jos Huisken
Extending Synchronization from Super-Threshold to Sub-threshold Region. 85-93 - Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny:
The Devolution of Synchronizers. 94-103
High Level Synthesis and Retiming
- John Hansen, Montek Singh:
A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems. 107-116 - Gennette Gill, Montek Singh:
Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems. 117-127 - Mario R. Casu
Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming. 128-137
Power-Performance Optimisation
- Christopher LaFrieda, Benjamin Hill, Rajit Manohar:
An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. 141-150 - Basit Riaz Sheikh, Rajit Manohar:
An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder. 151-162
Arbitration, Delay-Insensitivity, GasP
- Chao Yan, Mark R. Greenstreet, Jochen Eisinger:
Formal Verification of an Arbiter Circuit. 165-175 - Florent Ouchet, Katell Morin-Allory, Laurent Fesquet:
Delay Insensitivity Does Not Mean Slope Insensitivity! 176-184 - Swetha Mettala Gilla, Marly Roncken, Ivan E. Sutherland:
Long-Range GasP with Charge Relaxation. 185-195
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-27 21:35 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: