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SIGARCH Computer Architecture News 10(2), SIGPLAN Notices 17(4)

• 
  Justin R. Rattner:
  Hardware/Software Cooperation in the iAPX-423. 1
• 
  John L. Hennessy, Norman P. Jouppi, Forest Baskett, Thomas R. Gross, John Gill:
  Hardware/Software Tradeoffs for Increased Performance. 2-11
• 
  James W. Rymarczyk:
  Coding Guidelines for Pipelined Processors. 12-19
• 
  Richard K. Johnsson, John D. Wick:
  An Overview of the Mesa Processor Architecture. 20-29
• 
  Alan D. Berenbaum, Michael W. Condry, Priscilla M. Lu:
  The Operating System and Language Support Features of the BELLMAC-32 Microprocessor. 30-38
• 
  George Radin:
  The 801 Minicomputer. 39-47
• 
  David R. Ditzel, Hubert R. McLellan:
  Register Allocation for Free: The C Machine Stack Cache. 48-56
• 
  Samuel P. Harbison:
  An Architectural Alternative to Optimizing Compilers. 57-65
• 
  Butler W. Lampson:
  Fast Procedure Calls. 66-76
• 
  Douglas W. Jones:
  Systematic Protection Mechanism Design. 77-80
• 
  Karl Reed:
  On a General Property of Memory Mapping Tables. 81-86
• 
  Robert P. Cook, Nitin Donde:
  An Experiment to Improve Operand Addressing. 87-91
• 
  Akira Fusaoka, Masaharu Hirayama:
  Compiler Chip: A Hardware Implementation of Compiler. 92-95
• 
  B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt:
  Architectural Support for the Efficient Generation of Code for Horizontal Architectures. 96-99
• 
  Robert E. McLear, D. M. Scheibelhut, E. Tammaru:
  Guidelines for Creating a Debuggable Processor. 100-106
• 
  Maurice V. Wilkes:
  Hardware Support for Memory Protection: Capability Implementations. 107-116
• 
  Fred J. Pollack, George W. Cox, Dan W. Hammerstrom, Kevin C. Kahn, Konrad K. Lai, Justin R. Rattner:
  Supporting Ada Memory Management in the iAPX-432. 117-131
• 
  Jean-Paul Sansonnet, Michel Castan, Christian Percebois, D. Botella, J. Perez:
  Direct Execution of Lisp on a List-Directed Architecture. 132-139
• 
  Mark Scott Johnson:
  Some Requirements for Architectural Support of Software Debugging. 140-148
• 
  Cornelis A. Middelburg:
  The Effect of the PDP-11 Architecture on Code Generation for Chill. 149-157
• 
  Richard E. Sweet, James G. Sandman Jr.:
  Empirical Analysis of the Mesa Instruction Set. 158-166
• 
  Gene McDaniel:
  An Analysis of a Mesa Instruction Set Using Dynamic Instruction Frequencies. 167-176
• 
  Cheryl A. Wiecek:
  A Case Study of VAX-11 Instruction Set Usage for Compiler Execution. 177-184
• 
  Mamoru Maekawa, Ken Sakamura, Chiaki Ishikawa:
  Firmware Structure and Architectural Support for Monitors, Vertical Migration and User Microprogramming. 185-194
• 
  Noriyuki Kamibayashi, H. Ogawana, K. Nagayama, Hideo Aiso:
  Heart: An Operating System Nucleus Machine Implemented by Firmware. 195-204
• 
  Sudhir Ahuja, Abhaya Asthana:
  A Multi-Microprocessor Architecture with Hardware Support for Communication and Scheduling. 205-209

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last updated on 2025-01-14 21:20 CET by the dblp team

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