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13. ARC 2017: Delft, The Netherlands
- Stephan Wong, Antonio Carlos Schneider Beck, Koen Bertels, Luigi Carro:
Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings. Lecture Notes in Computer Science 10216, 2017, ISBN 978-3-319-56257-5
Adaptive Architectures
- Sensen Hu, Anthony Brandon, Qi Guo, Yizhuo Wang:
Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor. 3-15 - Álvaro Avelino, Valentin Obac Roda, Naim Harb, Carlos Valderrama, Glauberto Albuquerque, Paulo Da Cunha Possa:
LP-P2IP: A Low-Power Version of P1IP Architecture Using Partial Reconfiguration. 16-27 - Geraldo F. Oliveira, Paulo C. Santos, Marco A. Z. Alves
, Luigi Carro:
NIM: An HMC-Based Machine for Neuron Computation. 28-35 - Joost Hoozemans, Rolf Heij, Jeroen van Straten
VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications. 36-43
Embedded Computing and Security
- Christophe Bobda, Joshua Mead, Taylor J. L. Whitaker, Charles A. Kamhoua, Kevin A. Kwiat:
Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip. 47-59 - Nils Voss, Tobias Becker
Rapid Development of Gzip with MaxJ. 60-71 - Andreas Fiessler, Daniel Loebenberger, Sven Hager, Björn Scheuermann:
On the Use of (Non-)Cryptographic Hashes on FPGAs. 72-80 - Ngoc-Hung Nguyen, Sheraz Ali Khan
An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications. 81-89
Simulation and Synthesis
- Théotime Bollengier, Loïc Lagadec
Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach. 93-105 - Habib ul Hasan Khan, Diana Göhringer
FPGA Debugging with MATLAB Using a Rule-Based Inference System. 106-117 - Abdul Rafay Khatri, Ali Hayek, Josef Börcsök:
Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs. 118-128 - Muhammad Adeel Pasha, Umer Farooq, Muhammad Ali, Bilal Siddiqui:
A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable Architectures. 129-137
Design Space Exploration
- Peter Figuli, Weiqiao Ding, Shalina Percy Delicia Figuli, Kostas Siozios
Parameter Sensitivity in Virtual FPGA Architectures. 141-153 - Andreea-Ingrid Funie, Liucheng Guo, Xinyu Niu, Wayne Luk, Mark Salmon:
Custom Framework for Run-Time Trading Strategies. 154-167 - Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser:
Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation. 168-176 - Dimple Sharma, Victor Dumitriu, Lev Kirischian:
Architecture Reconfiguration as a Mechanism for Sustainable Performance of Embedded Systems in case of Variations in Available Power. 177-186
Fault Tolerance
- Ádria Barros de Oliveira, Lucas Antunes Tambara, Fernanda Lima Kastensmidt
Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC. 189-201 - André Flores dos Santos
Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs. 202-213
FPGA-Based Designs
- Mustapha Bouhali, Farid Shamani, Zine Elabadine Dahmane, Abdelkader Belaidi, Jari Nurmi
FPGA Applications in Unmanned Aerial Vehicles - A Review. 217-228 - Enrico Petraglio, Rick Wertenbroek
Genomic Data Clustering on FPGAs for Compression. 229-240 - Matthias Göbel, Ahmed Elhossini, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
A Quantitative Analysis of the Memory Architecture of FPGA-SoCs. 241-252
Neural Networks
- Ruizhe Zhao, Xinyu Niu, Yajie Wu, Wayne Luk, Qiang Liu:
Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms. 255-267 - Tomoya Fujii, Simpei Sato, Hiroki Nakahara
An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. 268-280 - Ruochun Jin, Jingfei Jiang, Yong Dou:
Accuracy Evaluation of Long Short Term Memory Network Based Language Model with Fixed-Point Arithmetic. 281-288 - Mostafa Morshedi, Hamid Noori:
FPGA Implementation of a Short Read Mapping Accelerator. 289-296
Languages and Estimation Techniques
- Paul Grigoras, Pavel Burovskiy, James Arram, Xinyu Niu, Kit Cheung, Junyi Xie, Wayne Luk:
dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs. 299-310 - Osvaldo Navarro, Jones Yudi Mori
A Machine Learning Methodology for Cache Recommendation. 311-322 - Jan Macheta, Agnieszka Dabrowska-Boruch
ArPALib: A Big Number Arithmetic Library for Hardware and Software Implementations. A Case Study for the Miller-Rabin Primality Test. 323-330
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