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20th Asian Test Symposium 2011: New Delhi, India
- Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1984-4
- Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
On Detecting Transition Faults in the Presence of Clock Delay Faults. 1-6 - Naghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty
, Pallav Gupta, Srinivas Patil:
Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip. 7-14 - Hyunjin Kim, Jacob A. Abraham:
On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test. 15-20 - Debesh Bhatta, Joshua W. Wells, Abhijit Chatterjee:
Time Domain Characterization and Test of High Speed Signals Using Incoherent Sub-sampling. 21-26 - Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Temperature Dependent Test Scheduling for Multi-core System-on-Chip. 27-32 - Xrysovalantis Kavousianos, Krishnendu Chakrabarty
Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands. 33-39 - Dong Xiang, Zhen Chen:
Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test Data. 40-45 - Vasileios Tenentes
Low Power Test-Compression for High Test-Quality and Low Test-Data Volume. 46-53 - Yasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara:
Multi-cycle Test with Partial Observation on Scan-Based BIST Structure. 54-59 - Mohammed Abdul Razzaq, Virendra Singh, Adit D. Singh:
SSTKR: Secure and Testable Scan Design through Test Key Randomization. 60-65 - Lilia Zaourar, Yann Kieffer, Chouki Aktouf:
An Innovative Methodology for Scan Chain Insertion and Analysis at RTL. 66-71 - Nastaran Nemati, Zainalabedin Navabi:
Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing. 72-77 - Ozgur Sinanoglu
Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing. 78-83 - Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer:
Low Power Decompressor and PRPG with Constant Value Broadcast. 84-89 - Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. 90-95 - Zhen Chen, Jia Li, Dong Xiang, Yu Huang:
Virtual Circuit Model for Low Power Scan Testing in Linear Decompressor-Based Compression Environment. 96-101 - Yoshinobu Higami, Hiroshi Furutani, Takao Sakai, Shuichi Kameyama, Hiroshi Takahashi:
Test Pattern Selection for Defect-Aware Test. 102-107 - Matthias Sauer, Jie Jiang, Alejandro Czutro, Ilia Polian, Bernd Becker
Efficient SAT-Based Search for Longest Sensitisable Paths. 108-113 - Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi:
Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware. 114-119 - Fang Bao, Ke Peng, Krishnendu Chakrabarty
On Generation of 1-Detect TDF Pattern Set with Significantly Increased SDD Coverage. 120-125 - Jae Chul Cha, Sandeep K. Gupta:
Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error Rates. 126-135 - D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. 136-141 - Paolo Bernardi
A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing. 142-147 - Behnam Khodabandeloo, Seyyed Alireza Hoseini, Sajjad Taheri, Mohammad Hashem Haghbayan, Mahmood Reza Babaei, Zainalabedin Navabi:
Online Test Macro Scheduling and Assignment in MPSoC Design. 148-153 - Jayaram Natarajan, Joshua W. Wells, Abhijit Chatterjee, Adit D. Singh:
Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations. 154-160 - Rance Rodrigues, Sandip Kundu:
An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors. 161-166 - Sarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram, Jim Grundy:
An Efficient 2-Phase Strategy to Achieve High Branch Coverage. 167-174 - Uros Legat, Anton Biasizzo, Franc Novak:
Soft Error Recovery Technique for Multiprocessor SOPC. 175-180 - Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu, Xiaowei Li:
Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC. 181-186 - Brandon Noia, Krishnendu Chakrabarty
Identification of Defective TSVs in Pre-Bond Testing of 3D ICs. 187-194 - Chih-Yun Pai, Ruei-Ting Gu, Bo-Chuan Cheng, Liang-Bi Chen
A Unified Interconnects Testing Scheme for 3D Integrated Circuits. 195-200 - Yi Zhao, S. Saqib Khursheed, Bashir M. Al-Hashimi:
Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs. 201-206 - Hongyan Zhang, Robert Wille
Improved Fault Diagnosis for Reversible Circuits. 207-212 - Abdullah Mumtaz, Michael E. Imhof, Stefan Holst, Hans-Joachim Wunderlich:
Embedded Test for Highly Accurate Defect Localization. 213-218 - Xiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng, Brady Benware:
On Using Design Partitioning to Reduce Diagnosis Memory Footprint. 219-225 - Gunjan Bhattacharya, Ilora Maity
Exploring Impact of Faults on Branch Predictors' Power for Diagnosis of Faulty Module. 226-231 - Eun Jung Jang, Jaeyong Chung
Post-Silicon Timing Validation Method Using Path Delay Measurements. 232-237 - Anvesh Komuravelli, Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta:
Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces. 238-243 - Steffen Zeidler, Christoph Wolf, Milos Krstic
Design of a Test Processor for Asynchronous Chip Test. 244-250 - Prasanjeet Das, Sandeep K. Gupta:
On Generating Vectors for Accurate Post-Silicon Delay Characterization. 251-260 - Jyotirmoy Saikia, Pramod Notiyath, Santosh Kulkarni, Ashok Anbalan, Rajesh Uppuluri, Tammy Fernandes, Parthajit Bhattacharya, Rohit Kapur:
Predicting Scan Compression IP Configurations for Better QoR. 261-266 - Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki:
Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. 267-272 - Hideyuki Ichihara, Yuka Iwamoto, Yuki Yoshikawa, Tomoo Inoue:
Test Compression Based on Lossy Image Encoding. 273-278 - Yang Yu, Gang Xi, Liyan Qiao:
Multiscan-based Test Data Compression Using UBI Dictionary and Bitmask. 279-284 - Alejandro Cook, Sybille Hellebrand, Thomas Indlekofer, Hans-Joachim Wunderlich:
Diagnostic Test of Robust Circuits. 285-290 - Po-Juei Chen, Wei-Li Hsu
An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects. 291-296 - Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya:
Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects. 297-302 - Xi Qian, Adit D. Singh, Abhijit Chatterjee:
Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations. 303-310 - Sreejit Chakravarty:
A Process Monitor Based Speed Binning and Die Matching Algorithm. 311-316 - Matthias Kirmse, Uwe Petersohn, Elief Paffrath:
Optimized Test Error Detection by Probabilistic Retest Recommendation Models. 317-322 - Baris Arslan, Alex Orailoglu:
Adaptive Test Framework for Achieving Target Test Quality at Minimal Cost. 323-328 - Yuntan Fang, Huawei Li
A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications. 329-334 - Umair Ishaq, Jihun Jung, Jaehoon Song, Sungju Park:
Efficient Use of Unused Spare Columns to Improve Memory Error Correcting Rate. 335-340 - Jaewon Cha, Ilwoong Kim, Sungho Kang:
New Fault Detection Algorithm for Multi-level Cell Flash Memroies. 341-346 - Said Hamdioui, Venkataraman Krishnaswami, Ijeoma Sandra Irobi, Zaid Al-Ars:
A New Test Paradigm for Semiconductor Memories in the Nano-Era. 347-352 - Nor Zaidi Haron, Said Hamdioui:
On Defect Oriented Testing for Hybrid CMOS/Memristor Memory. 353-358 - Manuel J. Barragan Asian, Rafaella Fiorelli
Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs. 359-364 - Alexios Spyronasios, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir:
On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study. 365-370 - Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Test and Diagnosis of Analog Circuits Using Moment Generating Functions. 371-376 - Nuno Guerreiro, Marcelino B. Santos
Mixed-Signal Fault Equivalence: Search and Evaluation. 377-382 - Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich:
Efficient BDD-based Fault Simulation in Presence of Unknown Values. 383-388 - Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Krishnendu Chakrabarty
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation. 389-394 - Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen
Automation of 3D-DfT Insertion. 395-400 - Stefano Di Carlo
MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches. 401-406 - Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Claude Thibeault:
Testing for Parasitic Memory Effect in SRAMs. 407-412 - Elena I. Vatajelu
Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric. 413-418 - Grzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek:
Fault Diagnosis in Memory BIST Environment with Non-march Tests. 419-424 - Atul Gupta, Ajay Kumar, Manas Chhabra:
Characterizing Pattern Dependent Delay Effects in DDR Memory Interfaces. 425-431 - Anshuman Chandra, Jyotirmoy Saikia, Rohit Kapur:
Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C). 432-437 - Keheng Huang, Yu Hu, Xiaowei Li, Gengxin Hua, Hongjin Liu, Bo Liu:
Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs. 438-443 - Haider A. F. Almurib
A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects. 444-450 - Chun-Chuan Chi, Erik Jan Marinissen
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. 451-456 - V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra:
Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs. 457-458 - Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri
Failure Analysis and Test Solutions for Low-Power SRAMs. 459-460 - K. Darbinyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
A Robust Solution for Embedded Memory Test and Repair. 461-462 - Manuel A. d'Abreu:
Nand Flash Memory - Product Trends, Technology Overview, and Technical Challenges. 463 - Masahiro Fujita:
High Level Verification and Its Use at Pos-Silicon Debugging and Patching. 464-469 - Paul D. Franzon
3D Specific Systems: Design and CAD. 470-473 - Brandon Noia, Krishnendu Chakrabarty
Testing and Design-for-Testability Techniques for 3D Integrated Circuits. 474-479 - Said Hamdioui, Mottaqiallah Taouil:
Yield Improvement and Test Cost Optimization for 3D Stacked ICs. 480-485 - Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst, Kaushik Roy:
Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost. 486-491 - Hidetoshi Onodera:
Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform Project. 492-495 - Norbert Wehn
Reliability: A Cross-Disciplinary and Cross-Layer Approach. 496-497 - Puneet Gupta
Underdesigned and Opportunistic Computing. 498-499 - Shray Khullar, Swapnil Bahl:
Power Aware Shift and Capture ATPG Methodology for Low Power Designs. 500-505 - Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Power-Aware Test Pattern Generation for At-Speed LOS Testing. 506-510 - Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer:
Power Aware Embedded Test. 511-516 - Debdeep Mukhopadhyay, Rajat Subhra Chakraborty:
Testability of Cryptographic Hardware and Detection of Hardware Trojans. 517-524 - Farrokh Ghani Zadegan
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints. 525-531 - Anton Tsertov
Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. 532-538 - Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Masaki Hashizume:
A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing. 539-544 - Carl Gray, David C. Keezer
Burst-Mode Transmission and Data Recovery for Multi-GHz Optical Packet Switching Network Testing. 545-551
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