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25th Asian Test Symposium 2016: Hiroshima, Japan
- 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016. IEEE Computer Society 2016, ISBN 978-1-5090-3809-1
Session 1A: Delay Test and Simulation
- Matthias Kampmann
, Sybille Hellebrand:
X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. 1-6 - Parameswaran Ramanathan, Kewal K. Saluja:
Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations. 7-12 - Irith Pomeranz, Sudhakar M. Reddy:
On the Switching Activity in Faulty Circuits During Test Application. 13-18 - Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte:
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. 19-24
Session 1B: Fault Diagnosis, Debug and Verification
- Sheng-Lin Lin, Cheng-Hung Wu, Kuen-Jong Lee:
Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis. 25-30 - Amir Masoud Gharehbaghi
A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality. 31-36 - Sayandeep Mitra, Moumita Das, Ansuman Banerjee, Kausik Datta, Tsung-Yi Ho
A Verification Guided Approach for Selective Program Transformations for Approximate Computing. 37-42 - Yingxin Qiu, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li
Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools. 43-48
Session 1C: Hardware Security
- Qingli Guo, Jing Ye, Yue Gong, Yu Hu, Xiaowei Li
Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm. 49-54 - Sujay Pandey, Sabyasachi Deyati, Adit D. Singh, Abhijit Chatterjee:
Noise-Resilient SRAM Physically Unclonable Function Design for Security. 55-60 - Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
On Test Points Enhancing Hardware Security. 61-66 - Sying-Jyan Wang
Side-Channel Attack on Flipped Scan Chains. 67-72
Session 2A: Special Session 1
- Mehdi Baradaran Tahoori, Krishnendu Chakrabarty:
Test and Reliability Issues in 2.5D and 3D Integration. 73 - Ran Wang, Krishnendu Chakrabarty
Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions. 74-79 - Shi-Yu Huang:
Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects. 80-85 - Shengcheng Wang, Ran Wang, Krishnendu Chakrabarty
Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs. 86-91
Session 2B: Analog and Mixed-Signal Test
- Hao-Chiao Hong
A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog Circuits. 92-95 - Barry John Muldrey
Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog Circuits. 96-101 - Mehrdad Heydarzadeh
Model-Free Testing of Analog Circuits. 102-106
Session 2C: Scan Test
- Jasvir Singh, Anuj Grover
Scan Chain Adaptation through ECO. 107-112 - Michael A. Kochte, Rafal Baranowski, Marcel Schaal, Hans-Joachim Wunderlich:
Test Strategies for Reconfigurable Scan Networks. 113-118 - Riccardo Cantoro
Test Time Minimization in Reconfigurable Scan Networks. 119-124
Session 3A: Industry Session (Oral Presentation)
- Masayuki Kawabata, Koji Asami, Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi:
Rectangular Waveform Generation with Harmonics Suppression. 125 - Jayalaxmi Satishkumar, Nagesh Vaidya:
Achieving Acceptable Bit Error Rate for 40 Gbps Link Using Signal Conditioning Techniques. 126 - Lai Pheng Tan, Shen Shen Lee, Kian Hui Wong:
Design and Implementation of EMIB Testing on 2.5D FPGA Transceiver. 127 - Hao Shen, Lance Shen, Pierce Xu, Wu Yang, Junna Zhong:
Application of Data Mining Based Scan Diagnosis Yield Analysis in a Foundry and Fabless Working Environment. 128 - Siaw Chen Lee, Soon Ee Ong:
rosTest: Universal Test Framework for Real-Time Operating System. 129 - Takeshi Mizushima, Kazuki Shirahata, Tasuku Fujibe, Hidenobu Matsumura, Daisuke Watanabe, Hiroyuki Mineo, Shin Masuda:
An Optical/Electrical Test System for 100-Gb/s Optical Interconnection Devices for High Volume Production. 130 - Hiroyuki Iwata, Jun Matsushima:
Multi-configuration Scan Structure for Various Purposes. 131
Session 3C: Fault Diagnosis
- Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng:
On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. 132-137 - M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman:
A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction. 138-143 - Laura Rodríguez Gómez, Hans-Joachim Wunderlich:
A Neural-Network-Based Fault Classifier. 144-149
Session 4B: Fault Modeling
- Eric Schneider, Hans-Joachim Wunderlich:
High-Throughput Transistor-Level Fault Simulation on GPUs. 150-155 - Hsuan-Wei Liu, Bing-Yang Lin, Cheng-Wen Wu
Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test. 156-160 - Khanh N. Dang
Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems. 161-166
Session 4C: Power-Aware Test
- Po-Fan Hou, Yi-Tsung Lin, Jiun-Lang Huang, Ann Shih, Zoe F. Conroy:
An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing. 167-172 - Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen:
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. 173-178 - Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker
On Optimal Power-Aware Path Sensitization. 179-184
Session 5A: Automatic Test Pattern Generation
- Harshad Dhotre, Mehdi Dehbashi, Ulrike Pfannkuchen, Klaus Hofmann:
Automated Optimization of Scan Chain Structure for Test Compression-Based Designs. 185-190 - Shingo Inuyama, Masayuki Arai, Kazuhiko Iwasaki:
Critical-Area-Aware Test Pattern Generation and Reordering. 191-196 - Harry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang
Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation. 197-202
Session 5B: Built-In Self-Test
- Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen:
A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. 203-208 - Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima:
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. 209-214
Session 5C: 3D IC Testing
- Jin-Cun Ye, Michael A. Kochte, Kuen-Jong Lee, Hans-Joachim Wunderlich:
Autonomous Testing for 3D-ICs with IEEE Std. 1687. 215-220 - Shi-Yu Huang, Chih-Chieh Zheng:
Die-to-Die Clock Skew Characterization and Tuning for 2.5D ICs. 221-226
Session 6A: Special Session 4: Managing Reliability of Integrated Circuits: Lifetime Metering and Design for Healing
- Sandip Kundu:
Managing Reliability of Integrated Circuits: Lifetime Metering and Design for Healing. 227 - Yong Zhao, Hans G. Kerkhoff:
Highly Dependable Multi-processor SoCs Employing Lifetime Prediction Based on Health Monitors. 228-233 - Song Bian, Michihiro Shintani
Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. 234-239 - Md. Nazmul Islam
Modeling Residual Lifetime of an IC Considering Spatial and Inter-Temporal Temperature Variations. 240-245
Session 6B: Fault Tolerance
- Atefe Dalirsani, Hans-Joachim Wunderlich:
Functional Diagnosis for Graceful Degradation of NoC Switches. 246-251 - Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Xiaolin Xu, Huaguo Liang:
Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology. 252-256 - Shih-Hsin Hu, Jacob A. Abraham:
Quality Aware Error Detection in 2-D Separable Linear Transformation. 257-262
Session 6C: Analog Circuits and High-Speed I/O Test
- Kazuki Shirahata, Takeshi Mizushima, Tasuku Fujibe, Hidenobu Matsumura, Tomoyuki Itakura, Masahiro Ishida, Daisuke Watanabe, Shin Masuda:
An Optical Interconnection Test Method Applicable to 100-Gb/s Transceivers Using an ATE Based Hardware. 263-268 - Te-Hui Chen, David C. Keezer
An Ultra-High-Speed Test Module and FPGA-Based Development Platform. 269-274 - Supriyo Srimani
Parametric Fault Detection in Analog Circuits: A Statistical Approach. 275-280
Session 7A: Memory Test and Reliability
- Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. 281-286 - Shyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume:
Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories. 287-292 - Takumi Uezono, Tadanobu Toba, Ken-ichi Shimbo, Fumihiko Nagasaki, Kenji Kawamura:
Evaluation Technique for Soft-Error Rate in Terrestrial Environment Utilizing Low-Energy Neutron Irradiation. 293-297
Session 7B: Dependable Systems
- Hao Luo, Mehrdad Heydarzadeh
Aging-Leakage Tradeoffs Using Multi-Vth Cell Library. 298-303 - Francesco Pellerey, Maksim Jenihhin
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. 304-309 - Warin Sootkaneung
Combined Impact of BTI and Temperature Effect Inversion on Circuit Performance. 310-315
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