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9th NorCAS 2023, Aalborg, Denmark
- IEEE Nordic Circuits and Systems Conference, NorCAS 2023, Aalborg, Denmark, October 31 - Nov. 1, 2023. IEEE 2023, ISBN 979-8-3503-3757-0
- Joonas Valkama, Mehdi Safarpour, Håkan Dicander, Zhongmin Deng, Andreas Burg
, Olli Silvén:
Low Power LDPC Decoding by Reliable Voltage Down-Scaling. 1-5 - Hamid Karrari, Pietro Andreani, Siyu Tan:
A 1.4 GS/s TI Pipelined-SAR analog-to-digital converter in 22-nm FDSOI CMOS. 1-5 - Francesco Gagliardi
Performance Modelling of Optimal Combination Algorithms Applied to Arbitrary Data Converter Architectures. 1-7 - Daniel Dik
Control Plane Isolation of Network Security Protocols using FPGA-SoC Trusted Execution Environment. 1-6 - Ali Hachem, Imane Belalchheb, Yoann Moline, Frédérick Carrel, Gwenolé Corre:
FPGA Implementation of MLP, 1D-CNN and TTTratio algorithms for Neutron/Gamma-ray Discrimination using Plastic Scintillator. 1-7 - Patrick Fath
A 370-nW Quad-Channel Multi-Mode Bio-Signal Acquisition AFE with 2.9-µVrms Input Noise. 1-5 - Eros Camacho-Ruiz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez
A complete SHA-3 hardware library based on a high efficiency Keccak design. 1-7 - Kari Siivonen, Joose Sainio, Alexandre Mercat
Tailored AVX2 Transform Kernels for Versatile Video Coding. 1-6 - Peter Koch
A First Experimental Study of Fixed-Point Approximate Arithmetic in Recursive Lattice Filters. 1-6 - Casper Cromjongh, Yongding Tian, H. Peter Hofstee, Zaid Al-Ars:
Tydi-Chisel: Collaborative and Interface-Driven Data-Streaming Accelerators. 1-7 - Ont-Derh Lin, Shi-Yu Huang:
Cell-Based Aging Sensor Using Built-In Speed Grading. 1-6 - Roni Hämäläinen, Henri Lunnikivi
Memory Mapped I/O Register Test Case Generator for Large Systems-on-Chip. 1-7 - Yasser Rezaeiyan
A low-noise high-linear wide dynamic-range MTJ-based magnetic field sensor. 1-4 - David Fosca Gamarra, Per Gunnar Kjeldsberg, Henrik Sundbeck:
Lens Flare Attenuation Accelerator Design with Deep Learning and High-Level Synthesis. 1-7 - Jere Rusanen, Negar Shabanzadeh, Aarno Pärssinen
Compensating Quadrature Hybrid Mismatch Effects in Integrated Balanced Power Amplifier. 1-5 - Topi Leppänen
AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management. 1-7 - Kimi Jokiniemi, Kaisa Ryynänen, Joni Vähä, Elmo Kankkunen, Kari Stadius, Jussi Ryynänen:
Active Wideband 55-100-GHz Downconversion Mixer in 22-nm FDSOI CMOS. 1-7 - Ruixing Yang, Yingge Chen, François Ladouceur, Nigel H. Lovell, Amr Al Abed, Torsten Lehmann:
Active Noise Cancelling Method for An Electro-Optical Detection System. 1-7 - Junchao Chen, Li Lu, Marko S. Andjelkovic, Markus Ulbricht, Milos Krstic
Adaptive Lock-Step System for Resilient Multiprocessing Architectures. 1-6 - Rikard Gannedahl, Henrik Sjöland
A mm-Wave Differential-to-Quadrature Frequency Tripler with Automatic Locking and Quadrature Correction. 1-6 - Olle Martinsson:
Implementation and Performance of a General Purpose Incremental Sigma-Delta Converter. 1-6 - Martti Forsell, Jussi Roivainen, Ville Leppänen
Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors. 1-7 - Sini Huemer, Ahmad Sadigh Baroughi
Approximation-aware Task Partitioning on an Approximate-Exact MPSoC (AxE). 1-7 - Johannes Kappes, Robert Kunzelmann
Effective Processor Model Generation from Instruction Set Simulator to Hardware Design. 1-7 - Jacopo Sini, Mohammadreza Amel Solouki
Guidelines for Implementing Control Flow Checking into Automotive Embedded Applications Developed with C Language. 1-6 - Samuel Boyle, Aksel Gunderson, Milica Orlandic:
High-level FPGA Design of Deep Learning Hyperspectral Anomaly Detection. 1-5 - Kaisa Ryynänen, Veeti Lahtinen, Santeri Porrasmaa
An Automated EM-Simulation Environment with Parameterized Layout Generation for Microwave Integrated Circuits. 1-6 - Fabian Kreß, Johannes Pfau
Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing. 1-7 - Ahmed M. Mohey
Toward All-Digital Time-Domain Neural Network Accelerators for In-Sensor Processing Applications. 1-6 - Sahibia Kaur Vohra, Alex Pappachen James, Mahendra Sakare
Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism. 1-7 - Mikael Henriksson, Oscar Gustafsson:
Streaming Matrix Transposition on FPGAs Using Distributed Memories. 1-6 - Kevin Kauth, Tim Stadtmann, Vida Sobhani
neuroAIx: FPGA Cluster for Reproducible and Accelerated Neuroscience Simulations of SNNs. 1-7 - Hans Jakob Damsgaard
Verification of Approximate Hardware Designs with ChiselVerify. 1-7 - Alvaro Cintas Canto, Mehran Mozaffari Kermani
Reliable Code-Based Post-Quantum Cryptographic Algorithms through Fault Detection on FPGA. 1-5 - Luca Pezzarossa, Martin Schoeberl
Transitioning to Chisel in University Education: Experiences and Lessons Learned. 1-7 - Behnam Abdollahi
A Low-Power Current-Reuse Self-Biased Regulated-Cascode TIA in 130nm SiGe BiCMOS for Low-Noise and High Data Rate Applications. 1-7 - Pawel Dzialo, Erik Vd. Boom, Per Lindgren:
SyncRim - A modern Simulator for Synchronous Circuits implemented in Rust. 1-6 - Marek Jahnke, Lucas Bublitz, Ulf Kulau:
Performance Evaluation of PicoRV32 RISC-V Softcore for Resource-Constrained Devices. 1-6 - Mohd. Tasleem Khan, Oscar Gustafsson:
Analyzing Step-Size Approximation for Fixed-Point Implementation of LMS and BLMS Algorithms. 1-5 - Qirui Hua
Deep Learning-Enhanced Parameter Extraction for Equivalent Circuit Modeling in Electrochemical Impedance Spectroscopy. 1-6 - Negar Shabanzadeh, Aarno Pärssinen
Time-varying distortion contribution analysis of single-transistor mixers. 1-5 - Michael Köfinger, Patrick Fath, Harald Pretl:
An Open-Source Micro-Watt 130-dB Delta-Sigma Modulator with 600mVpp Input Range for DC-Coupled Biosignal Acquisition. 1-6 - Julian Haase, Sebastian Jaster
Enhancing Robustness and Reliability of Networks-on-Chip with Network Coding. 1-7 - Johannes Pfau
Co-Simulating Region-Based Dynamic Voltage Scaling for FPGA Architecture Design. 1-7 - Antoine Gautier, Benoît Larras, Olev Märtens, Deepu John
Evaluation of Power-of-two Quantization for Multiplier-less Near-Memory and In-Memory Computing Schemes for Biomedical Applications. 1-5 - Wei Cao
Ultra Low Power ASK Demodulator/Manchester Decoder for Biomedical Applications. 1-4 - Manish Pundir, Bipul Kumar Singh, Ninad Bandu Kamble, Ambika Prasad Shah:
High-Performance Floating Resistor-based Ring Amplifier for Switched Capacitor Circuits. 1-6 - Fabian Seiler
An IMPLY-based Semi-Serial Approximate In-Memristor Adder. 1-7 - Mohammad Javad Karimi, Junyan Qian, Catherine Dehollain, Alexandre Schmid:
Design of a Dual-Band Wireless Power and Data Transfer Coil for Multisite Biomedical Implants. 1-6
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