More Web Proxy on the site http://driver.im/

default search action

combined dblp search
author search
venue search
publication search

ask others

"Design Optimization of a High-Speed, Area-Efficient and Low-Power ..."

Shoichi Masui et al. (2005)

> Home

Details and statistics

DOI: 10.1093/IETELE/E88-C.4.576

access: closed

type: Journal Article

metadata version: 2020-04-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ieicet/MasuiMTT05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/MasuiMTT05
Shoichi Masui, Kenji Mukaida, Masahiko Takenaka, Naoya Torii:
Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm. IEICE Trans. Electron. 88-C(4): 576-581 (2005)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.