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"An Optimized BIST Architecture for FPGA Look-Up Table Testing."

Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi (2006)

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DOI: 10.1109/ISVLSI.2006.24

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/isvlsi/YarandiAN06
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  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/YarandiAN06
Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi:
An Optimized BIST Architecture for FPGA Look-Up Table Testing. ISVLSI 2006: 420-421

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