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"Transistor-level Sizing and Timing Verification of Domino Circuits in the ..."

Abhijit Dharchoudhury et al. (1997)

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DOI: 10.1109/ICCD.1997.628861

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning:
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD 1997: 143-148

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