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"A Technique Using PUFs for Protecting Circuit Layout Designs against ..."

Dai Yamamoto et al. (2014)

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DOI: 10.1007/978-3-319-09843-2_13

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii:
A Technique Using PUFs for Protecting Circuit Layout Designs against Reverse Engineering. IWSEC 2014: 158-173

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