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Charles H.-P. Wen
Charles Hung-Pin Wen
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- affiliation: National Chiao Tung University, Department of Electrical and Computer Engineering, Hsinchu, Taiwan
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2020 – today
- 2024
- [j28]Alan Y.-P. Lee, Michael I.-C. Wang
, Chi-Hsiang Hung
PS-IPS: Deploying Intrusion Prevention System with machine learning on programmable switch. Future Gener. Comput. Syst. 152: 333-342 (2024) - [j27]Michael I.-C. Wang
Assessing the impact of communication delays for Autonomous Intersection Management systems. Veh. Commun. 49: 100829 (2024) - [c69]Alan S.-M. Liu, Lowry P.-T. Wang, Charles H.-P. Wen, Herming Chiueh:
LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets. ITC 2024: 407-416 - [c68]Ralf E.-H. Yee, Nicholas Y.-J. Su, Lowry P.-T. Wang, Charles H.-P. Wen
Temperature-Insensitive Soft-Error-Tolerant Flip-Flop Design For Automotive Electronics. VTS 2024: 1-7 - 2023
- [j26]Michael I.-C. Wang
Hierarchical Cooperation and Load Balancing for Scalable Autonomous Vehicle Routing in Multi-Access Edge Computing Environment. IEEE Trans. Veh. Technol. 72(6): 6959-6971 (2023) - [c67]Sam M.-H. Hsiao, Amy H.-Y. Tsai, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen
Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs. ITC 2023: 276-285 - 2022
- [j25]Yu-Jie Lin, Chi-Hsiang Hung
Real-Time In-Network Microburst Mitigation on Programmable Switch. IEEE Access 10: 2446-2456 (2022) - [j24]Dave Y.-W. Lin
Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop. IEEE Trans. Computers 71(5): 1008-1020 (2022) - [j23]Michael I.-C. Wang
Roadrunner+: An Autonomous Intersection Management Cooperating with Connected Autonomous Vehicles and Pedestrians with Spillback Considered. ACM Trans. Cyber Phys. Syst. 6(1): 5:1-5:29 (2022) - [j22]Aaron C.-W. Liang
A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1341-1354 (2022) - [c66]Zhong-Li Tang, Chia-Wei Liang, Ming-Hsien Hsiao, Charles H.-P. Wen
SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process. DAC 2022: 865-870 - [c65]Sam M.-H. Hsiao, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen
Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies. ITC 2022: 128-136 - [c64]Jiun-Cheng Tsai
Timing-Critical Path Analysis in Circuit Designs Considering Aging with Signal Probability. ITC-Asia 2022: 37-42 - [c63]Hsin-Fu Chang, Michael I.-C. Wang, Chi-Hsiang Hung, Charles H.-P. Wen
Enabling Malware Detection with Machine Learning on Programmable Switch. NOMS 2022: 1-5 - [c62]Linyih Teng, Chi-Hsiang Hung, Charles H.-P. Wen
P4SF: A High-Performance Stateful Firewall on Commodity P4-Programmable Switch. NOMS 2022: 1-5 - [c61]Zong-Hua Tsai, Aaron C.-W. Liang, Charles H.-P. Wen
SlewFTA: Functional Timing Analysis Considering Slew Propagation. VLSI-DAT 2022: 1-4 - 2021
- [j21]Dave Y.-W. Lin, Charles H.-P. Wen
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability. ACM Trans. Design Autom. Electr. Syst. 26(6): 50:1-50:12 (2021) - [c60]Aaron C.-W. Liang, Hsuan-Ming Huang, Charles H.-P. Wen
Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes. DATE 2021: 1829-1834 - [c59]John Z.-L. Tang, Dave Y.-W. Lin, Ralf E.-H. Yee, Charles H.-P. Wen
AMSER-FF: Area-Minimized Soft-Error-Recoverable Flip-Flop for Radiation Hardening. ITC-Asia 2021: 1-6 - 2020
- [j20]Denny C.-Y. Wu
Speeding Up Functional Timing Analysis by Concise Formulation of Timed Characteristic Functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5281-5294 (2020) - [j19]Dave Y.-W. Lin
DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1030-1042 (2020) - [c58]Gary K.-C. Huang, Dave Y.-W. Lin, John Z.-L. Tang, Charles H.-P. Wen
SDPTA: Soft-Delay-aware Pattern-based Timing Analysis and Its Path-Fixing Mechanism. ATS 2020: 1-6 - [c57]Willy Y.-W. Hsu, Jiun-Cheng Tsai
Profit-Driven Service-Chain Deployment For EDA Requests On Private Cloud. CloudNet 2020: 1-4 - [c56]Hsueh-Hong Kang, Chi-Hsiang Hung, Charles H.-P. Wen
SAFCast: Smart Inter-Datacenter Multicast Transfer with Deadline Guarantee by Store-And-Forwarding. INFOCOM 2020: 1034-1042 - [c55]Michael I.-C. Wang
Roadrunner: Autonomous Intersection Management with Dynamic Lane Assignment. ITSC 2020: 1-7 - [c54]Herming Chiueh, Chia-Hsiang Yang, Charles H.-P. Wen
Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS. VLSI-DAT 2020: 1-2
2010 – 2019
- 2019
- [j18]Louis Y.-Z. Lin
P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings. IEEE Access 7: 6816-6830 (2019) - [j17]Yang Xu
Dynamic Switch Migration in Distributed Software-Defined Networks to Achieve Controller Load Balance. IEEE J. Sel. Areas Commun. 37(3): 515-529 (2019) - [c53]Cheng-Hsien Shen, Aaron C.-W. Liang, Charles C.-H. Hsu, Charles H.-P. Wen
FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging. ITC 2019: 1-10 - [c52]Ashkan Aghdai, Michael I.-C. Wang
In-network Congestion-aware Load Balancing at Transport Layer. NFV-SDN 2019: 1-6 - [c51]Hsueh-Hong Kang, I-Chih Wang
Parcel-Fit: Low Network-Overhead Service-Chain Deployment for Better Datacenter Performance. NFV-SDN 2019: 1-7 - 2018
- [j16]Louis Y.-Z. Lin
Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation. IEEE Access 6: 49269-49281 (2018) - [j15]Chien-Hui Liao
SVM-Based Dynamic Voltage Prediction for Online Thermally Constrained Task Scheduling in 3-D Multicore Processors. IEEE Embed. Syst. Lett. 10(2): 49-52 (2018) - [j14]Chia-Ling Lynn Chang, Charles H.-P. Wen
Accurate performance evaluation of VLSI designs with selected CMOS process parameters. IET Circuits Devices Syst. 12(1): 116-123 (2018) - [j13]Chien-Hui Liao
Online task scheduler in 3D-MCPs with TADVA. IET Comput. Digit. Tech. 12(2): 44-52 (2018) - [c50]Pin-Ru Jhao, Denny C.-Y. Wu, Charles H.-P. Wen:
Skew-Aware Functional Timing Analysis Against Setup Violation for Post-Layout Validation. ITC-Asia 2018: 67-72 - [c49]I-Chih Wang
Improving Quality of Experience of Service-Chain Deployment for Multiple Users. IWQoS 2018: 1-6 - [i1]Ashkan Aghdai, Michael I.-C. Wang, Yang Xu, Charles H.-P. Wen, H. Jonathan Chao:
In-network Congestion-aware Load Balancing at Transport Layer. CoRR abs/1811.09731 (2018) - 2017
- [j12]Chien-Hui Liao, Charles H.-P. Wen
An Online Thermal-Pattern-Aware Task Scheduler in 3D Multi-Core Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2901-2910 (2017) - [c48]Yu-Lun Su, I-Chih Wang
FASIC: A Fast-Recovery, Adaptively Spanning In-Band Control Plane in Software-Defined Network. GLOBECOM 2017: 1-6 - [c47]Yuwen Dave Lin, Charles H.-P. Wen, Herming Chiueh:
Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops. ACM Great Lakes Symposium on VLSI 2017: 197-202 - [c46]Jack S.-Y. Lin, Louis Y.-Z. Lin, Ryan H.-M. Huang, Charles H.-P. Wen:
Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax? ACM Great Lakes Symposium on VLSI 2017: 251-256 - [c45]Ying-Feng Wu, Yu-Lun Su, Charles H.-P. Wen
TVM: Tabular VM migration for reducing hop violations of service chains in cloud datacenters. ICC 2017: 1-6 - [c44]Denny C.-Y. Wu, Pin-Ru Jhao, Charles H.-P. Wen
Accelerating functional timing analysis with encoding duplication removal and redundant state propagation. ICCAD 2017: 117-122 - [c43]Yuan-Ming Pai, Charles H.-P. Wen
SLA-driven Ordered Variable-width Windowing for service-chain deployment in SDN datacenters. ICOIN 2017: 167-172 - [c42]Charles Chia-Hao Hsu, Charles H.-P. Wen:
Speeding up power verification by merging equivalent power domains in RTL design with UPF. ITC-Asia 2017: 168-173 - [c41]Tsung-Han Lei, Yao-Tsung Hsu, I-Chih Wang
Deploying QoS-assured service function chains with stochastic prediction models on VNF latency. NFV-SDN 2017: 1-6 - 2016
- [j11]Hsuan-Ming Huang, Charles H.-P. Wen
Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults - From Device to Circuit Level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4): 586-597 (2016) - [c40]Louis Y.-Z. Lin, Charles H.-P. Wen:
Speed binning with high-quality structural patterns from functional timing analysis (FTA). ASP-DAC 2016: 238-243 - [c39]Hsuan-Ming Huang, Yuwen Lin, Charles H.-P. Wen:
Fast-yet-accurate variation-aware current and voltage modelling of radiation-induced transient fault. DATE 2016: 211-216 - [c38]Cheng Suo, I-Chen Tsai, Charles H.-P. Wen
ERIC: Economical & reconfigurable hybrid-band control for software-defined datacenter network. ICOIN 2016: 214-219 - [c37]Kuan-Wei Li, Po-Han Huang, Charles H.-P. Wen:
Reducing network cost of minimal-migration based VM management in cloud datacenters. NOF 2016: 1-3 - 2015
- [j10]Ryan H.-M. Huang, Dennis K.-H. Hsu, Charles H.-P. Wen
A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs. J. Electron. Test. 31(2): 181-192 (2015) - [j9]Chia-Ling Lynn Chang, Charles H.-P. Wen
Demystifying Iddq Data With Process Variation for Automatic Chip Classification. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1175-1179 (2015) - [j8]Chien-Hui Liao, Charles H.-P. Wen
Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2719-2723 (2015) - [c36]Po-Han Huang, Kuan-Wei Li, Charles H.-P. Wen:
NACHOS: Network-aware chains orchestration selection for NFV in SDN datacenter. CloudNet 2015: 205-208 - [c35]Jasper C. C. Chang, Ryan H.-M. Huang, Louis Y.-Z. Lin, Charles H.-P. Wen
TA-FTA: transition-aware functional timing analysis with a four-valued encoding. DAC 2015: 165:1-165:6 - [c34]Chien-Hui Liao, Charles H.-P. Wen, Krishnendu Chakrabarty:
An online thermal-constrained task scheduler for 3D multi-core processors. DATE 2015: 351-356 - [c33]Kuan-Tsen Kuo, Charles H.-P. Wen
SWF: Segmented Wildcard Forwarding for flow migration in OpenFlow datacenter networks. ICC 2015: 313-318 - [c32]Chien-Hui Liao, Yu-Ze Lin, Charles H.-P. Wen:
Dynamic voltage assignment for thermal-constrained task scheduler on 3D multi-core processors. VLSI-DAT 2015: 1-4 - 2014
- [c31]Jerry C. Y. Ku, Ryan H.-M. Huang, Louis Y.-Z. Lin, Charles H.-P. Wen:
Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation. ASP-DAC 2014: 664-669 - [c30]Ryan H.-M. Huang, Charles H.-P. Wen
Advanced Soft-Error-Rate (SER) Estimation with Striking-Time and Multi-Cycle Effects. DAC 2014: 24:1-24:6 - [c29]Kevin P. Y. Huang, Charles H.-P. Wen, Herming Chiueh:
Flexible Parallelized Empirical Mode Decomposition in CUDA for Hilbert Huang Transform. HPCC/CSS/ICESS 2014: 1125-1133 - [c28]Shao-Heng Wang, Patrick P.-W. Huang, Charles H.-P. Wen
EQVMP: Energy-efficient and QoS-aware virtual machine placement for software defined datacenter networks. ICOIN 2014: 220-225 - [c27]Hunta H.-W. Wang, Louis Y.-Z. Lin, Ryan H.-M. Huang, Charles H.-P. Wen
CASTA: CUDA-Accelerated Static Timing Analysis for VLSI Designs. ICPP 2014: 192-200 - [c26]Sung S.-Y. Hsueh, Ryan H.-M. Huang, Charles H.-P. Wen
TASSER: A temperature-aware statistical soft-error-rate analysis framework for combinational circuits. ISQED 2014: 529-534 - 2013
- [j7]Hsuan-Ming Huang, Charles H.-P. Wen
Fast-Yet-Accurate Statistical Soft-Error-Rate Analysis Considering Full-Spectrum Charge Collection. IEEE Des. Test 30(2): 77-86 (2013) - [j6]Christina C.-H. Liao, Allen W.-T. Chen, Louis Y.-Z. Lin, Charles H.-P. Wen
Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1170-1174 (2013) - [j5]Austin C.-C. Chang, Ryan H.-M. Huang, Charles H.-P. Wen
CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1837-1848 (2013) - [c25]Louis Y.-Z. Lin, Christina C.-H. Liao, Charles H.-P. Wen:
Synthesizing multiple scan chains by cost-driven spectral ordering. ASP-DAC 2013: 540-545 - [c24]Wei-Chu Lin, Chien-Hui Liao, Kuan-Tsen Kuo, Charles H.-P. Wen
Flow-and-VM Migration for Optimizing Throughput and Energy in SDN-Based Cloud Datacenter. CloudCom (1) 2013: 206-211 - [c23]Wei-Chu Lin, Gen-Hen Liu, Kuan-Tsen Kuo, Charles H.-P. Wen:
D2ENDIST-FM: Flow migration in routing of OpenFlow-based cloud networks. CloudNet 2013: 170-174 - [c22]Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra:
Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step. DATE 2013: 454-457 - [c21]Chien-Hui Christina Liao, Kuan-Wei Lee, Ting-Hua Chen, Che-Chen Chang, Charles H.-P. Wen:
Fall Detection by a SVM-Based Cloud System with Motion Sensors. EMC/HumanCom 2013: 37-45 - [c20]Cosette Y. H. Lin, Ryan H.-M. Huang, Charles H.-P. Wen, Austin C.-C. Chang:
Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs. VLSI-DAT 2013: 1-4 - 2012
- [j4]Y.-H. Chen, C.-L. Chang, Charles H.-P. Wen
Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow. IET Comput. Digit. Tech. 6(3): 186-193 (2012) - [j3]Huan-Kai Peng, Hsuan-Ming Huang, Yu-Hsin Kuo, Charles H.-P. Wen
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs. ACM Trans. Design Autom. Electr. Syst. 17(1): 9:1-9:24 (2012) - [c19]Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra:
An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology. ASP-DAC 2012: 163-168 - [c18]Gen-Hen Liu, Charles H.-P. Wen, Li-Chun Wang
D2ENDIST: Dynamic and disjoint ENDIST-based layer-2 routing algorithm for cloud datacenters. GLOBECOM 2012: 1611-1616 - [c17]Xin-Tian Wu, Kai-Hua Hsu, Lynn C.-L. Chang, Charles H.-P. Wen:
Spatial-correlation-aware soft error rate analysis using quasi-importance sampling. VLSI-DAT 2012: 1-4 - 2011
- [j2]Chen-Yuan Kao, Chien-Hui Liao, Charles H.-P. Wen
Diagnosing Multiple Byzantine Open-Segment Defects Using Integer Linear Programming. J. Electron. Test. 27(6): 723-739 (2011) - 2010
- [c16]Yu-Shin Kuo, Huan-Kai Peng, Charles H.-P. Wen:
Monte-Carlo-based statistical soft error rate (SSER) analysis for the deep sub-micron era. ISCAS 2010: 3673-3676 - [c15]Yu-Hsin Kuo, Huan-Kai Peng, Charles H.-P. Wen:
Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models. ISQED 2010: 831-838
2000 – 2009
- 2009
- [c14]Huan-Kai Peng, Charles H.-P. Wen, Jayanta Bhadra:
On soft error rate analysis of scaled CMOS designs - A statistical perspective. ICCAD 2009: 157-163 - [c13]Chia-Ling Chang, Charles H.-P. Wen
Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning. ITC 2009: 1-8 - [c12]Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen
Portable simulation/emulation stimulus on an industrial-strength SoC. ITC 2009: 1 - [c11]Chen-Yuan Kao, Chien-Hui Liao, Charles H.-P. Wen
An ILP-Based Diagnosis Framework for Multiple Open-Segment Defects. MTV 2009: 69-72 - 2008
- [c10]Chia-Ling Lynn Chang, Charles H.-P. Wen
Mining Unreachable Cross-Timeframe State-Pairs for Bounded Sequential Equivalence Checking. MTV 2008: 33-38 - 2007
- [c9]Charles H.-P. Wen
An incremental learning framework for estimating signal controllability in unit-level verification. ICCAD 2007: 250-257 - 2006
- [j1]Charles H.-P. Wen
Simulation-Based Functional Test Generation for Embedded Processors. IEEE Trans. Computers 55(11): 1335-1343 (2006) - [c8]Onur Guzey, Charles H.-P. Wen
Extracting a simplified view of design functionality via vector simulation. HLDVT 2006: 195-202 - [c7]Onur Guzey, Charles H.-P. Wen
Extracting a Simplified View of Design Functionality Based on Vector Simulation. Haifa Verification Conference 2006: 34-49 - [c6]Charles H.-P. Wen, Onur Guzey, Li-C. Wang
Simulation-based functional test justification using a decision-digram-based Boolean data miner. ICCD 2006: 300-307 - 2005
- [c5]Leonard Lee, Sean H. Wu, Charles H.-P. Wen, Li-C. Wang:
On Generating Tests to Cover Diverse Worst-Case Timing Corners. DFT 2005: 415-426 - [c4]Charles H.-P. Wen
Simulation-based functional test generation for embedded processors. HLDVT 2005: 3-10 - [c3]Charles H.-P. Wen
Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology. ITC 2005: 10 - [c2]Charles H.-P. Wen
Simulation Data Mining for Functional Test Pattern Justification. MTV 2005: 76-83 - [c1]Charles H.-P. Wen, Li-C. Wang
On A Software-Based Self-Test Methodology and Its Application. VTS 2005: 107-113
Coauthor Index
Chien-Hui Liao
aka: Chien-Hui Christina Liao
aka: Chien-Hui Christina Liao
Michael I.-C. Wang
aka: I-Chih Wang
aka: I-Chih Wang
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