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Pedro Echeverría
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2010 – 2019
- 2013
- [j4]Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo
, Bogdan Pasca
Floating-Point Exponentiation Units for Reconfigurable Computing. ACM Trans. Reconfigurable Technol. Syst. 6(1): 4:1-4:15 (2013) - [j3]Pedro Echeverría, Marisa López-Vallejo
High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator. J. Signal Process. Syst. 71(2): 105-109 (2013) - 2011
- [j2]Pedro Echeverría, Marisa López-Vallejo
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs. Microprocess. Microsystems 35(6): 535-546 (2011)
2000 – 2009
- 2009
- [c6]Pedro Echeverría, Marisa López-Vallejo
Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs. ICECS 2009: 423-426 - 2008
- [j1]Pedro Echeverría Aramendi, José L. Ayala
Power Considerations in Banked CAMs: A Leakage Reduction Approach. VLSI Design 2008: 674259:1-674259:7 (2008) - [c5]Pedro Echeverría, David B. Thomas, Marisa López-Vallejo
An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC 2008: 219-230 - [c4]Miguel Angel Sánchez, Pedro Echeverría, Francisco Mansilla, Marisa López-Vallejo
Designing Highly Parameterized Hardware using xHdl. FDL 2008: 78-83 - [c3]Ignacio Herrera-Alzu, Miguel Angel Sánchez, Marisa López-Vallejo
Experimental methodology for power characterization of FPGAs. ICECS 2008: 582-585 - [c2]Pedro Echeverría, Marisa López-Vallejo
Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach. ICECS 2008: 1296-1299 - 2006
- [c1]Pedro Echeverría, José Luis Ayala, Marisa López-Vallejo
Leakage Energy Reduction in Banked Content Addressable Memories. ICECS 2006: 1196-1199
Coauthor Index
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