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2020 – today

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2024
[j14]
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Vu Trung Duong Le, Hoai-Luan Pham, Thi Hong Tran, Yasuhiko Nakashima:
Flexible and Energy-Efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-Based IoT Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 319-330 (2024)
[c29]
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Pham Hoai Luan, Hai Hau Nguyen, Vu Trung Duong Le, Thi Diem Tran, Tuan Hai Vu, Thi Hong Tran, Yasuhiko Nakashima:
MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements. COOL CHIPS 2024: 1-6
2023
[j13]
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  - journals/cryptography/KoyamaTFBT23
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Atsuki Koyama, Van Chuong Tran, Manato Fujimoto, Vo Nguyen Quoc Bao, Thi Hong Tran:
A Decentralized COVID-19 Vaccine Tracking System Using Blockchain Technology. Cryptogr. 7(1): 13 (2023)
[j12]
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Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications. IEEE Des. Test 40(5): 15-25 (2023)
[j11]
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  - journals/sensors/TranLT23
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Van Duy Tran, Duc Khai Lam, Thi Hong Tran:
Hardware-Based Architecture for DNN Wireless Communication Models. Sensors 23(3): 1302 (2023)
[c28]
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Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima:
Efficient and High-Speed CGRA Accelerator for Cryptographic Applications. candar 2023: 189-195
[c27]
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Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Quoc Duy Nam Nguyen, Thi Sang Duong, Yasuhiko Nakashima:
Versatile Resource-shared Cryptographic Accelerator for Multi-Domain Applications. ICICDT 2023: 104-107
[c26]
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Quoc Duy Nam Nguyen, Thi Hong Tran, Tadashi Nakano:
Optimizing Parkinson's Disease Classification and Severity Assessment Using Dense Multiscale Sample Entropy and Hybrid Feature Selection. ICIT 2023: 64-69
[c25]
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Van Duy Tran, Duc Khai Lam, Thi Hong Tran:
Robust Deep Learning Approaches for Wireless Communication Systems. ICIT 2023: 120-125
[c24]
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  - conf/kse/LePDTNN23
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Vu Trung Duong Le, Hoai Luan Pham, Thi Sang Duong, Thi Hong Tran, Quoc Duy Nam Nguyen, Yasuhiko Nakashima:
RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms. KSE 2023: 1-6
[c23]
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  - conf/mcsoc/DuongPLTINTN23
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Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Diem Tran, Ren Imamura, Quoc Duy Nam Nguyen, Thi Hong Tran, Yasuhiko Nakashima:
Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission. MCSoC 2023: 419-425
[c22]
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Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima:
High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing. MCSoC 2023: 576-583
[c21]
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Pham Hoai Luan, Thi Sang Duong, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima:
Energy-Efficient Unified Multi-Hash Coprocessor for Securing IoT Systems Integrating Blockchain. MWSCAS 2023: 355-359
[c20]
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  - conf/rivf/DuongPLITN23
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Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Ren Imamura, Thi Hong Tran, Yasuhiko Nakashima:
Small-Footprint Reconfigurable Heterogeneous Cryptographic Accelerator for Fog Computing. RIVF 2023: 124-129
[c19]
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Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima:
Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing. SOCC 2023: 1-6
2022
[j10]
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  - journals/access/PhamTDN22
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Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator. IEEE Access 10: 11830-11845 (2022)
[j9]
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Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator. IEEE Access 10: 68740-68754 (2022)
[c18]
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  - conf/ipps/PhamTDN22
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Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration. IPDPS Workshops 2022: 671-678
[c17]
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  - conf/mwscas/LuanaTLN22
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Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A High-Efficiency FPGA-based BLAKE-256 Accelerator for Securing Blockchain Networks. MWSCAS 2022: 1-4
[c16]
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  - conf/sbcci/LeLTN22
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Vu Trung Duong Le, Pham Hoai Luan, Thi Hong Tran, Yasuhiko Nakashima:
CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining. SBCCI 2022: 1-6
[c15]
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  - conf/sbcci/LuanTLN22
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Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications. SBCCI 2022: 1-6
2021
[j8]
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  - journals/access/TranPN21
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Thi Hong Tran, Hoai Luan Pham, Yasuhiko Nakashima:
A High-Performance Multimem SHA-256 Accelerator for Society 5.0. IEEE Access 9: 39182-39192 (2021)
[j7]
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  - journals/access/DuongTPLN21
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Vu Trung Duong Le, Thi Hong Tran, Hoai Luan Pham, Duc Khai Lam, Yasuhiko Nakashima:
MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security. IEEE Access 9: 168383-168396 (2021)
[j6]
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  - journals/tcasI/TranPPN21
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Thi Hong Tran, Hoai Luan Pham, Tri Dung Phan, Yasuhiko Nakashima:
BCA: A 530-mW Multicore Blockchain Accelerator for Power-Constrained Devices in Securing Decentralized Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4245-4258 (2021)
[c14]
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  - conf/coolchips/PhanPTN21
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Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima:
High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory. COOL CHIPS 2021: 1-3
2020
[j5]
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  - journals/access/PhamTPDLN20
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Hoai Luan Pham, Thi Hong Tran, Tri Dung Phan, Vu Trung Duong Le, Duc Khai Lam, Yasuhiko Nakashima:
Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining. IEEE Access 8: 139634-139646 (2020)

2010 – 2019

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2019
[c13]
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  - conf/apcc/LeNTN19
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Dinh-Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima:
Run-Length Limited Decoding for Visible Light Communications: A Deep Learning Approach. APCC 2019: 496-501
[c12]
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  - conf/icbc2/NguyenPTHN19
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Van-Cam Nguyen, Hoai-Luan Pham, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima:
Digitizing Invoice and Managing VAT Payment Using Blockchain Smart Contract. IEEE ICBC 2019: 74-77
[c11]
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  - conf/iccbn/HoangTN19
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Dai Long Hoang, Thi Hong Tran, Yasuhiko Nakashima:
Hardware Implementation of CORDIC Based Physical Layer Phase Decryption for IEEE 802.11ah. ICCBN 2019: 17-21
[c10]
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  - conf/rivf/CuongHK19
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Chong Nhat Cuong, Thi Hong Tran, Duc Khai Lam:
Hardware Implementation of the Efficient SOR-Based Massive MIMO Detection for Uplink. RIVF 2019: 1-6
[i2]
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  - journals/corr/abs-1904-00832
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Duc Phuc Nguyen, Dinh-Dung Le, Thi Hong Tran, Yasuhiko Nakashima:
Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems. CoRR abs/1904.00832 (2019)
2018
[j4]
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  - journals/ieicet/LeNTN18
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Dinh-Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima:
Log-Likelihood Ratio Calculation Using 3-Bit Soft-Decision for Error Correction in Visible Light Communication Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2210-2212 (2018)
[c9]
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  - conf/globecom/PhamTN18
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Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima:
A Secure Remote Healthcare System for Hospital Using Blockchain Smart Contract. GLOBECOM Workshops 2018: 1-6
[i1]
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  - journals/corr/abs-1805-00359
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Duc Phuc Nguyen, Dinh-Dung Le, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima:
Hardware Implementation of A Non-RLL Soft-decoding Beacon-based Visible Light Communication Receiver. CoRR abs/1805.00359 (2018)
2017
[j3]
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  - journals/jcm/NguyenTN17
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Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima:
A Multi-Mode Error-Correction Solution Based on Split-Concatenation for Wireless Sensor Nodes. J. Commun. 12(2): 130-136 (2017)
2016
[c8]
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  - conf/apccas/KatoTN16
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Hiromasa Kato, Thi Hong Tran, Yasuhiko Nakashima:
ASIC design of a low-complexity K-best Viterbi decoder for IoT applications. APCCAS 2016: 396-399
[c7]
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  - conf/coolchips/TranKNN16
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Thi Hong Tran, Soichiro Kanagawa, Duc Phuc Nguyen, Yasuhiko Nakashima:
ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system. COOL Chips 2016: 1-3
[c6]
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  - conf/ic-nc/KatoSFKTTN16
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Hiromasa Kato, Satoshi Shimaya, Keisuke Fujimoto, Tomoya Kameda, Thi Hong Tran, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis. CANDAR 2016: 375-380
2014
[j2]
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  - journals/ejwcn/TranNO14
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Thi Hong Tran, Yuhei Nagao, Hiroshi Ochi:
Algorithm and hardware design of a 2D sorter-based K-best MIMO decoder. EURASIP J. Wirel. Commun. Netw. 2014: 93 (2014)
[c5]
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  - conf/apccas/HongyoTLON14
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Reina Hongyo, Thi Hong Tran, Leonardo Lanante, Hiroshi Ochi, Yuhei Nagao:
A design of low complex log likelihood ratio for MIMO decoder using the bit shift. APCCAS 2014: 727-730
[c4]
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Thi Hong Tran, Hiroshi Ochi, Yuhei Nagao:
A 4 × 4 multiplier-divider-less K-best MIMO decoder up to 2.7 Gbps. ISCAS 2014: 1696-1699
[c3]
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  - conf/iscit/TranNOK14
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Thi Hong Tran, Yuhei Nagao, Hiroshi Ochi, Masayuki Kurosaki:
ASIC design of 7.7 Gbps multi-mode LDPC decoder for IEEE 802.11ac. ISCIT 2014: 259-263
[c2]
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  - conf/vtc/TranON14
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Thi Hong Tran, Hiroshi Ochi, Yuhei Nagao:
A 2D Sorter-Based K-Best Algorithm for High Order Modulation MIMO Systems. VTC Fall 2014: 1-5
2013
[j1]
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  - journals/ieicet/TranLNO13
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Thi Hong Tran, Leonardo Lanante, Yuhei Nagao, Hiroshi Ochi:
Hardware Design of Multi Gbps RC4 Stream Cipher. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(11): 2120-2127 (2013)
2012
[c1]
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  - conf/iscas/TranLNKO12
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Thi Hong Tran, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi:
Hardware Implementation of High Throughput RC4 algorithm. ISCAS 2012: 77-80

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