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Xiaoyan Gui
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2020 – today
- 2024
- [j7]Shuaizhe Ma
, Nianquan Ran, Xi Liu, Yifei Xia
Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 5221-5234 (2024) - [c26]Xin Lei, Xinhao Zheng, Yiqian Nie, Xinke Huang, Kun Fu, Yukun He, Xiaoyan Gui:
A 4×4 5-6GHz CMOS Wi-Fi Transceiver Front-End for Fiber-to-the-Room with Analog Beamforming Achieving 27dBm 1024 QAM MCS11 EIRP and -45dB EVM Floor. CICC 2024: 1-2 - [c25]Yifei Xia
An Integrated Burst-Mode 2R Receiver Employing Fast Residual Offset Canceller for XGS-PON in 40-nm CMOS. CICC 2024: 1-2 - 2023
- [j6]Xiaoyan Gui
A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique. IET Circuits Devices Syst. 17(1): 13-28 (2023) - [c24]Yukun He, Zhao Yuan, Kanan Wang, Renjie Tang, Yunxiang He, Dan Li, Li Geng, Xiaoyan Gui:
A 28/56 Gb/s NRZ/PAM-4 Dual-Mode Transceiver in 28-nm CMOS. ICTA 2023: 138-139 - 2022
- [j5]Hamed Mosalam
A 54-68 GHz Power Amplifier With Improved Linearity and Efficiency in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(1): 40-44 (2022) - [j4]Xiaochuan Zhou, Xiaoyan Gui
A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 359-363 (2022) - [c23]Chen Tan, Wei Huang, Yonghui Fan, Jing Li, Chuanhao Yu, Wenbo Shi, Shiti Huang, Zhenyu Yin, Chenfan Cao, Lei Jing, Zhixiong Ren, Xiaoyan Gui, Bing Zhang, Dan Li, Li Geng:
A 10/2.5-Gb/s Hyper-Supplied CMOS Low-Noise Burst-Mode TIA with Loud Burst Protection and Gearbox Automatic Offset Cancellation for XGS-PON. CICC 2022: 1-2 - 2021
- [j3]Li Dong
A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array. Microelectron. J. 113: 105109 (2021) - [c22]Qi Zhang, Xiongshi Luo, Zhenghao Li, Dongfan Xu, Siqiang Zhu, Leiming Wang, Zhenjiang Mao, Xiaoyan Gui, Dan Li, Hongyu Yu, Quan Pan:
A 720-mVpp 224-Gb/s PAM4 Optical Receiver with Multiple Peaking Techniques in 130-nm SiGe BiCMOS. APCCAS 2021: 249-252 - [c21]Kanan Wang, Kuantian Guo, Haoran Yang, Renjie Tang, Zhen Zhao, Dan Li, Xiaoyan Gui:
A 130-GBaud 2: 1 Analog Multiplexer in 130-nm SiGe BiCMOS. ICTA 2021: 135-136 - [c20]Chuanhao Yu, Zhenyu Yin, Chenfan Cao, Shiti Huang, Quan Pan, Xiaoyan Gui, Li Geng, Dan Li:
A 100GBaud Optical Receiver Front-End in 90nm SiGe BiCMOS. ICTA 2021: 224-225 - [c19]Wei Huang, Xiangwen Liu, Yongjun Shi, Dan Li, Bing Zhang, Xiaoyan Gui, Li Geng:
A Low-Noise Stacked Differential Optical Receiver in 0.18-μm CMOS. MWSCAS 2021: 890-893 - 2020
- [j2]Xiaoyan Gui
Low-Supply Sensitivity LC VCOs With Complementary Varactors. IEEE Trans. Very Large Scale Integr. Syst. 28(7): 1589-1599 (2020) - [c18]Bingjun Tang
A Full-duplex Transceiver with Integrated Active Quasi-circulator Achieving Self-interference RF Cancellation over Wide Bandwidth. ICTA 2020: 9-10 - [c17]Renjie Tang, Kanan Wang, Dan Li, Li Geng, Xiaoyan Gui:
A 100-Gb/s PAM-4 CTLE in 28-nm CMOS with Coarse-Fine Gain Adjustment. ICTA 2020: 92-93 - [c16]Xiangwen Liu, Yihua Zhang, Chuangji Zhou, Dan Li, Xiaoyan Gui, Li Geng:
A 16Gb/s Triple-Mode Driver in 0.18μm CMOS Technology. ICTA 2020: 96-97 - [c15]Dan Li, Shengwei Gao, Yongjun Shi, Xiaoyan Gui, Nan Qi, Zhiyong Li, Quan Pan, Patrick Chiang, Li Geng:
A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [c14]Li Dong, Zhechong Lan, Xiaoyan Gui, Chengyang He, Youze Xin, Ken Li, Li Geng:
A Multi-Channel 1.52 µVrms Front End with Orthogonal Frequency Chopping for Neural Recording Applications. APCCAS 2019: 389-392 - [c13]Yihua Zhang, Zhuoqi Guo, Yang Xie, Dan Li, Shiquan Fan, Xiaoyan Gui, Li Geng:
A Stacked 4×25 Gb/s Optical Receiver in 28 nm CMOS with 0.154 mW/Gb/s Power Efficiency. ISCAS 2019: 1-4 - 2018
- [c12]Xiaoyan Gui, Kai Li, Xiaoli Wang, Li Geng:
A Dual-Path Open-Loop CMOS Slew-Rate Controlled Output Driver with low PVT Variation. MWSCAS 2018: 274-277 - [c11]Bingjun Tang
Design of A Low-Supply Sensitivity LC VCO with Complementary Varactors. MWSCAS 2018: 282-285 - 2015
- [c10]Peng Gao, Zicheng Liu, Xiaoyan Gui:
Modeling and design of a 0.8-30 GHz tunable inductor-less divide-by-2 frequency divider with digital frequency calibration. MWSCAS 2015: 1-4 - [c9]Han Zhou, Xiaoyan Gui, Peng Gao:
Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC. SoCC 2015: 175-179 - 2013
- [j1]Xiaoyan Gui, Michael M. Green:
Design of CML Ring Oscillators With Low Supply Sensitivity. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(7): 1753-1763 (2013) - [c8]Hua Dang, Ruoyuan Qu, Zhiming Chen, Xiaoyan Gui, Xinghua Wang:
A Whole Integrated System for Detection of Neural Signal and Wireless Transmission. GreenCom/iThings/CPScom 2013: 1779-1783 - [c7]Hua Dang, Zicheng Liu, Xiaoyan Gui, Shun'an Zhong:
A Compensated Technique for 2.5-GHz Ring-Oscillator-Based PLL used in Wireless Transmission. GreenCom/iThings/CPScom 2013: 1795-1798 - [c6]Hua Dang, Lei Zhang, Zhiming Chen, Xiaoyan Gui, Xinghua Wang:
Circuit Design of Analog Front-End for Neural Signal Detection. GreenCom/iThings/CPScom 2013: 1817-1819 - [c5]Hua Dang, Xiao Li, Zhiming Chen, Xiaoyan Gui, Xinghua Wang, Shun'an Zhong:
Design and Implementation of a Circuit System for Neural Signal Detection. GreenCom/iThings/CPScom 2013: 1825-1828 - [c4]Shiwen Li, Hua Dang, Peng Gao, Xiaoyan Gui, Zhiming Chen, Xinghua Wang, Shun'an Zhong:
Design and Implementation of a CMOS 1Gsps 5bit Flash ADC with Offset Calibration. GreenCom/iThings/CPScom 2013: 1829-1833 - [c3]Ruoyuan Qu, Na Liu, Zhe Guo, Xinghua Wang, Xiaoyan Gui:
Wireless circuits design for neural recording application. TSP 2013: 596-599 - 2011
- [c2]Xiaoyan Gui, Michael M. Green:
Nonlinearities in frequency dividers. ECCTD 2011: 532-535 - 2010
- [c1]Xiaoyan Gui, Michael M. Green:
High-speed CMOS ring oscillators with low supply sensitivity. CICC 2010: 1-4
Coauthor Index
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