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Alireza Hodjat
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2000 – 2009
- 2007
- [j4]Alireza Hodjat, Lejla Batina, David Hwang, Ingrid Verbauwhede
:
HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor. Integr. 40(1): 45-51 (2007) - 2006
- [j3]David D. Hwang, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. IEEE J. Solid State Circuits 41(4): 781-792 (2006) - [j2]Alireza Hodjat, Ingrid Verbauwhede
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors. IEEE Trans. Computers 55(4): 366-372 (2006) - [c13]Lejla Batina, Alireza Hodjat, David Hwang, Kazuo Sakiyama, Ingrid Verbauwhede
Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers. FPL 2006: 1-4 - 2005
- [c12]Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede:
Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP. CHES 2005: 106-118 - [c11]Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede:
Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. CHES 2005: 354-365 - [c10]Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. DAC 2005: 222-227 - [c9]Alireza Hodjat, David Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede:
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. ACM Great Lakes Symposium on VLSI 2005: 60-63 - [c8]Alireza Hodjat, David Hwang, Ingrid Verbauwhede
A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks. ITCC (1) 2005: 538-543 - [p1]Ingrid Verbauwhede
Security for Ambient Intelligent Systems. Ambient Intelligence 2005: 199-221 - 2004
- [j1]Alireza Hodjat, Ingrid Verbauwhede
High-Throughput Programmable Cryptocoprocessor. IEEE Micro 24(3): 34-45 (2004) - [c7]Alireza Hodjat, Ingrid Verbauwhede
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA. FCCM 2004: 308-309 - [c6]Patrick Schaumont
Embedded Software Integration for Coarse-Grain Reconfigurable Systems. IPDPS 2004 - [c5]Alireza Hodjat, Ingrid Verbauwhede
Minimum Area Cost for a 30 to 70 Gbits/s AES Processor. ISVLSI 2004: 83-88 - [c4]Alireza Hodjat, Patrick Schaumont
Architectural Design Features of a Programmable High Throughput AES Coprocessor. ITCC (2) 2004: 498-502 - [c3]Herwin Chan, Alireza Hodjat, Jun Shi, Richard D. Wesel, Ingrid Verbauwhede
Streaming Encryption for a Secure Wavelength and Time Domain Hopped Optical Network. ITCC (2) 2004: 578-582 - 2003
- [c2]David D. Hwang, Bo-Cheng Lai, Patrick Schaumont
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system. DAC 2003: 60-65 - [c1]Patrick Schaumont
Testing ThumbPod: Softcore bugs are hard to find. HLDVT 2003: 77-82
Coauthor Index
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