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Nan-Chi Chou
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2010 – 2019
- 2011
- [j5]Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham:
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 167-179 (2011)
2000 – 2009
- 2009
- [c13]Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng:
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. DAC 2009: 166-171 - 2007
- [j4]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng:
Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 959-969 (2007) - 2005
- [c12]Peter Suaris, Dongsheng Wang, Nan-Chi Chou:
A practical cut-based physical retiming algorithm for field programmable gate arrays. ASP-DAC 2005: 1027-1030 - [c11]Yuzheng Ding, Peter Suaris, Nan-Chi Chou:
The effect of post-layout pin permutation on timing. FPGA 2005: 41-50 - [c10]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris:
Improving the efficiency of static timing analysis with false paths. ICCAD 2005: 527-531 - [c9]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris:
Unified quadratic programming approach for mixed mode placement. ISPD 2005: 193-199 - 2004
- [c8]Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou:
Incremental physical resynthesis for timing optimization. FPGA 2004: 99-108 - [c7]Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris:
Fast adders in modern FPGAs. FPGA 2004: 250 - 2003
- [c6]Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu:
An algebraic multigrid solver for analytical placement with layout based clustering. DAC 2003: 794-799 - [c5]Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou:
A physical retiming algorithm for field programmable gate arrays. FPGA 2003: 247 - [c4]Dongsheng Wang, Peter Suaris, Nan-Chi Chou:
A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. PATMOS 2003: 511-519
1990 – 1999
- 1995
- [j3]Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof:
Local ratio cut and set covering partitioning for huge logic emulation systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1085-1092 (1995) - [j2]Nan-Chi Chou, Chung-Kuan Cheng:
On general zero-skew clock net construction. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 141-146 (1995) - 1994
- [j1]So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu:
A multi-probe approach for MCM substrate testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 110-121 (1994) - [c3]Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof:
Circuit Partitioning for Huge Logic Emulation Systems. DAC 1994: 244-249 - 1993
- [c2]Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku:
Performance-driven partitioning using retiming and replication. ICCAD 1993: 296-299 - 1992
- [c1]So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu:
An optimal probe testing algorithm for the connectivity verification of MCM substrates. ICCAD 1992: 264-267
Coauthor Index
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