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Suleyman Tosun
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2020 – today
- 2024
- [j23]Furkan Nacar, Alperen Cakin, Selma Dilek
, Suleyman Tosun
Neuron grouping and mapping methods for 2D-mesh NoC-based DNN accelerators. J. Parallel Distributed Comput. 193: 104949 (2024) - [j22]Alperen Cakin, Selma Dilek, Suleyman Tosun:
Energy-aware application mapping methods for mesh-based hybrid wireless network-on-chips. J. Supercomput. 80(11): 15582-15612 (2024) - [j21]Yusuf Yamak, Suleyman Tosun, Murat Aydos:
DICEguard: enhancing DICE security for IoT devices with periodic memory forensics. J. Supercomput. 80(13): 19824-19844 (2024) - 2023
- [j20]Selma Dilek
Simulated annealing-based high-level synthesis methodology for reliable and energy-aware application specific integrated circuit designs with multiple supply voltages. Int. J. Circuit Theory Appl. 51(10): 4897-4938 (2023) - 2022
- [j19]Selma Dilek
A High-Level Synthesis Methodology for Energy and Reliability-Oriented Designs. IEEE Trans. Computers 71(1): 161-174 (2022) - [j18]Kaouther Gasmi, Selma Dilek
A survey on computation offloading and service placement in fog computing-based IoT. J. Supercomput. 78(2): 1983-2014 (2022) - [j17]Inan Kazanci
Computation Power and Energy Optimized Task Allocation in Internet of Things. IEEE Trans. Netw. Serv. Manag. 19(4): 4424-4433 (2022) - [c23]Selma Dilek
Towards QoS-Aware Resource Allocation in Fog Computing: A Theoretical Model. ISNCC 2022: 1-6 - 2021
- [j16]Anil Ipek, Suleyman Tosun
HAFTA: Highly adaptive fault-tolerant routing algorithm for two-dimensional network-on-chips. Concurr. Comput. Pract. Exp. 33(21) (2021) - [j15]Yigitcan Nalci, Pinar Kullu
ILP formulation and heuristic method for energy-aware application mapping on 3D-NoCs. J. Supercomput. 77(3): 2667-2680 (2021) - [c22]Nurettin Bölücü, Suleyman Tosun:
Q-Learning-based Routing Algorithm for 3D Network-on-Chips. DDECS 2021: 33-36 - 2020
- [j14]Akin Gokalan, Suleyman Tosun
Library Characterization of Arithmetic Circuits for Reliability-Aware Designs in SRAM-Based FPGAs. J. Electron. Test. 36(6): 743-756 (2020) - [j13]Pinar Kullu
Mapping application-specific topology to mesh topology with reconfigurable switches. IET Comput. Digit. Tech. 14(1): 9-16 (2020)
2010 – 2019
- 2019
- [j12]Suleyman Tosun
Genetic Algorithm-based Reliability Optimization for High-Level Synthesis. J. Circuits Syst. Comput. 28(3): 1950039:1-1950039:26 (2019) - [j11]Pinar Kullu
Energy-aware and fault-tolerant custom topology design method for network-on-chips. Nano Commun. Networks 19: 54-66 (2019) - [c21]Pinar Kullu
MARM-GA: Mapping Applications to Reconfigurable Mesh using Genetic Algorithm. DSD 2019: 13-18 - [c20]Murat Berk
Number Analysis and Operator Detection in Telecommunication Systems. ISNCC 2019: 1-5 - 2018
- [j10]Enan A. Khalil
Evolutionary task allocation in Internet of Things-based application domains. Future Gener. Comput. Syst. 86: 121-133 (2018) - [j9]Suleyman Tosun
Energy-aware partitioning of fault-tolerant irregular topologies for 3D network-on-chips. J. Supercomput. 74(9): 4842-4863 (2018) - 2017
- [c19]Tohid Taghizad Gogjeh Yaran, Suleyman Tosun:
Improving combinational circuit resilience against soft errors via selective resource allocation. DDECS 2017: 12-15 - [c18]Arash Barzinmehr
Energy-aware application-specific topology generation for 3D Network-on-Chips. DDECS 2017: 84-87 - 2016
- [c17]Serif Yesil, Suleyman Tosun, Özcan Özturk:
FPGA implementation of a fault-tolerant application-specific NoC design. DTIS 2016: 1-6 - 2015
- [j8]Özcan Özturk, Ismail Akturk, Ismail Kadayif, Suleyman Tosun:
Energy reduction in 3D NoCs through communication optimization. Computing 97(6): 593-609 (2015) - [j7]Suleyman Tosun, Vahid Babaei Ajabshir, Ozge Mercanoglu, Özcan Özturk:
Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1495-1508 (2015) - [j6]Suleyman Tosun, Özcan Özturk, Erencan Ozkan, Meltem Ozen:
Application mapping algorithms for mesh-based network-on-chip architectures. J. Supercomput. 71(3): 995-1017 (2015) - [c16]Ozge Mercanoglu Sincan, Vahid Babaei Ajabshir, Hacer Yalim Keles, Suleyman Tosun:
Moving object detection by a mounted moving camera. EUROCON 2015: 1-6 - 2014
- [c15]Suleyman Tosun, Vahid Babaei Ajabshir, Ozge Mercanoglu, Özcan Özturk:
Fault-Tolerant Irregular Topology Design Method for Network-on-Chips. DSD 2014: 631-634 - [c14]Vahid Babaei Ajabshir, Suleyman Tosun:
Fault-Tolerant Routing for Irregular-Topology-Based Network-on-Chips. CANDAR 2014: 123-129 - 2012
- [j5]Suleyman Tosun, Yilmaz Ar
Application-specific topology generation algorithms for network-on-chip design. IET Comput. Digit. Tech. 6(5): 318-333 (2012) - [j4]Suleyman Tosun:
Energy- and reliability-aware task scheduling onto heterogeneous MPSoC architectures. J. Supercomput. 62(1): 265-289 (2012) - 2011
- [j3]Suleyman Tosun:
Cluster-based application mapping method for Network-on-Chip. Adv. Eng. Softw. 42(10): 868-874 (2011) - [j2]Suleyman Tosun:
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs. J. Syst. Archit. 57(1): 69-78 (2011) - 2010
- [j1]Suleyman Tosun:
FIT: Fast Irregular Topology generation algorithm for application specific NoCs. IEICE Electron. Express 7(15): 1132-1138 (2010)
2000 – 2009
- 2007
- [i1]Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie:
Reliability-Centric High-Level Synthesis. CoRR abs/0710.4684 (2007) - 2006
- [c13]Sirzat Kahramanli, Suleyman Tosun:
A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization. CDES 2006: 10-16 - [c12]Suleyman Tosun, Mahmut T. Kandemir, Hakduran Koc:
Using Task Recomputation During Application Mapping in Parallel Embedded Architectures. CDES 2006: 29-35 - [c11]Ozcan Ozturk, Mahmut T. Kandemir, Suleyman Tosun:
An ILP based approach to address code generation for digital signal processors. ACM Great Lakes Symposium on VLSI 2006: 37-42 - [c10]Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun:
Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors. ICPADS (1) 2006: 383-390 - [c9]Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk:
An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors. ISCIS 2006: 267-276 - [c8]Hakduran Koc, Suleyman Tosun, Ozcan Ozturk, Mahmut T. Kandemir:
Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems. ISVLSI 2006: 448-449 - 2005
- [c7]Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie:
Reliability-Centric High-Level Synthesis. DATE 2005: 1258-1263 - [c6]Guilin Chen, Mahmut T. Kandemir, Suleyman Tosun, Ugur Sezer:
Reliability-Conscious Process Scheduling under Performance Constraints in FPGA-Based Embedded Systems. IPDPS 2005 - [c5]Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung:
An ILP Formulation for Reliability-Oriented High-Level Synthesis. ISQED 2005: 364-369 - [c4]Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung:
Reliability-Centric Hardware/Software Co-Design. ISQED 2005: 375-380 - [c3]Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Özcan Özturk:
Constraint-based Code mapping for heterogeneous Chip multiprocessors. SoCC 2005: 89-90 - [c2]Özcan Özturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun:
On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression. SoCC 2005: 175-178 - 2003
- [c1]Suleyman Tosun, Hakduran Koc, Nazanin Mansouri:
Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs. VLSI 2003: 382-
Coauthor Index
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last updated on 2024-12-02 21:33 CET by the dblp team
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