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Nathaniel Ross Pinckney
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2020 – today
- 2024
- [c24]Christopher Batten
, Nathaniel Ross Pinckney
PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs. MLCAD 2024: 10:1-10:17 - [i4]Nathaniel Ross Pinckney, Christopher Batten, Mingjie Liu, Haoxing Ren, Brucek Khailany:
Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks. CoRR abs/2408.11053 (2024) - 2023
- [c23]Rongjian Liang
Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation. DAC 2023: 1-2 - [c22]Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren:
Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation. ICCAD 2023: 1-8 - [i3]Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren:
VerilogEval: Evaluating Large Language Models for Verilog Code Generation. CoRR abs/2309.07544 (2023) - [i2]Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Ross Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, Kishor Kunal, Xiaowei Li, Hao Liu, Stuart F. Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P. Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren:
ChipNeMo: Domain-Adapted LLMs for Chip Design. CoRR abs/2311.00176 (2023) - 2021
- [j7]Yakun Sophia Shao, Jason Clemons
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64(6): 107-116 (2021) - [c21]Nathaniel Ross Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany:
IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs. ICCAD 2021: 1-9 - [i1]Steve Dai, Alicia Klinefelter, Haoxing Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Ross Pinckney, Brucek Khailany:
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. CoRR abs/2102.06326 (2021) - 2020
- [j6]Brian Zimmer
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55(4): 920-932 (2020)
2010 – 2019
- 2019
- [c20]Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany:
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. ASYNC 2019: 27-35 - [c19]Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium 2019: 1-24 - [c18]Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD 2019: 1-8 - [c17]Yakun Sophia Shao, Jason Clemons
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO 2019: 14-27 - [c16]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits 2019: 300- - 2018
- [j5]Yiqun Zhang
iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor. IEEE J. Solid State Circuits 53(2): 619-631 (2018) - [c15]Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons
A modular digital VLSI flow for high-productivity SoC design. DAC 2018: 72:1-72:6 - 2017
- [j4]Nathaniel Ross Pinckney
Impact of FinFET on Near-Threshold Voltage Scalability. IEEE Des. Test 34(2): 31-38 (2017) - 2016
- [c14]Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. DAC 2016: 76:1-76:6 - [c13]Nathaniel Ross Pinckney, Dennis Sylvester, David T. Blaauw:
Supply boosting for high-performance processors in flip-chip packages. ESSCIRC 2016: 473-476 - [c12]Yiqun Zhang, Mahmood Khayatzadeh, Kaiyuan Yang
8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor. ISSCC 2016: 160-162 - 2015
- [c11]Jingcheng Wang, Nathaniel Ross Pinckney, David T. Blaauw, Dennis Sylvester:
Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect. A-SSCC 2015: 1-4 - [c10]Suyoung Bang, Jae-sun Seo, Inhee Lee, Seokhyeon Jeong, Nathaniel Ross Pinckney, David T. Blaauw, Dennis Sylvester, Leland Chang:
A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple. VLSIC 2015: 336- - 2014
- [c9]Bharan Giridhar, Nathaniel Ross Pinckney, Dennis Sylvester, David T. Blaauw:
13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS. ISSCC 2014: 242-243 - 2013
- [j3]Matthew Fojtik, David Fick, Yejoong Kim
Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction. IEEE J. Solid State Circuits 48(1): 66-81 (2013) - [j2]Nathaniel Ross Pinckney, Ronald G. Dreslinski, Korey Sewell, David Fick, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Limits of Parallelism and Boosting in Dim Silicon. IEEE Micro 33(5): 30-37 (2013) - [c8]Gyouho Kim, Mahmood Barangi, Zhiyoong Foo, Nathaniel Ross Pinckney, Suyoung Bang, David T. Blaauw, Dennis Sylvester:
A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation. ISSCC 2013: 480-481 - 2012
- [j1]Korey Sewell, Ronald G. Dreslinski, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das
Swizzle-Switch Networks for Many-Core Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 278-294 (2012) - [c7]Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems. PACT 2012: 75-86 - [c6]Nathaniel Ross Pinckney, Korey Sewell, Ronald G. Dreslinski, David Fick, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Assessing the performance limits of parallelized near-threshold computing. DAC 2012: 1147-1152 - [c5]Ronald G. Dreslinski, Korey Sewell, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das
Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems. Hot Chips Symposium 2012: 1-44 - [c4]Matthew Fojtik, David Fick, Yejoong Kim
Bubble Razor: An architecture-independent approach to timing-error detection and correction. ISSCC 2012: 488-490
2000 – 2009
- 2008
- [c3]Philip Amberg, Nathaniel Ross Pinckney, David Money Harris:
Parallel high-radix Montgomery multipliers. ACSCC 2008: 772-776 - [c2]Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips:
A MIPS R2000 implementation. DAC 2008: 102-107 - 2007
- [c1]Nathaniel Ross Pinckney, David Money Harris:
Parallelized radix-4 scalable montgomery multipliers. SBCCI 2007: 306-311
Coauthor Index
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