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O. Sam Nakagawa
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2000 – 2009
- 2002
- [j1]Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu:
Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 799-805 (2002) - 2001
- [c9]Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie:
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. ISQED 2001: 185-190 - [c8]Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa:
Instruction Prediction for Step Power Reduction. ISQED 2001: 211-216 - 2000
- [c7]Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He:
Clocktree RLC Extraction with Efficient Inductance Modeling. DATE 2000: 522-526 - [c6]Zhiping Yu, Dan Yergeau, Robert W. Dutton, O. Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie:
Full Chip Thermal Simulation. ISQED 2000: 145-150 - [c5]Shen Lin, Norman Chang, O. Sam Nakagawa:
Quick On-Chip Self- and Mutual-Inductance Screen. ISQED 2000: 513- - [c4]Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He:
Ramp Up/Down Functional Unit to Reduce Step Power. PACS 2000: 13-24
1990 – 1999
- 1999
- [c3]Lei He, Norman Chang, Shen Lin, O. Sam Nakagawa:
An efficient inductance modeling for on-chip interconnects. CICC 1999: 457-460 - 1997
- [c2]Norman Chang, Valery Kanevsky, O. Sam Nakagawa, Khalid Rahmat, Soo-Young Oh:
Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect. ICCD 1997: 720-725 - 1996
- [c1]Soo-Young Oh, Khalid Rahmat, O. Sam Nakagawa, John Moll:
A Scaling Scheme and Optimization Methodology for Deep Sub-Micron Interconnect. ICCD 1996: 320-325
Coauthor Index
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