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James H. Mulligan Jr.
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1990 – 1999
- 1997
- [j8]Tolga Soyata
, Eby G. Friedman, James H. Mulligan Jr.:
Incorporating interconnect, register, and clock distribution delays into the retiming process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 105-120 (1997) - 1995
- [c2]Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.:
Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. ISCAS 1995: 1748-1751 - 1994
- [j7]Ramon S. Co, James H. Mulligan Jr.:
Optimization of phase-locked loop performance in data recovery systems. IEEE J. Solid State Circuits 29(9): 1022-1034 (1994) - 1993
- [j6]Yeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.:
Multiple training concept for back-propagation neural networks for use in associative memories. Neural Networks 6(8): 1169-1175 (1993) - [c1]Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.:
Integration of Clock Skew and Register Delays into a Retiming Algorithm. ISCAS 1993: 1483-1486 - 1991
- [j5]Yeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.:
Guaranteed recall of all training pairs for bidirectional associative memory. IEEE Trans. Neural Networks 2(6): 559-567 (1991) - [j4]Eby G. Friedman, James H. Mulligan Jr.:
Clock frequency and latency in synchronous digital systems. IEEE Trans. Signal Process. 39(4): 930-934 (1991) - 1990
- [j3]Yeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.:
Two coding strategies for bidirectional associative memory. IEEE Trans. Neural Networks 1(1): 81-92 (1990) - [j2]Yeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.:
On multiple training for bidirectional associative memory. IEEE Trans. Neural Networks 1(3): 275-276 (1990)
1950 – 1959
- 1959
- [j1]James H. Mulligan Jr.:
A Figure of Merit for Single-Pass Data Recording Systems. IRE Trans. Electron. Comput. 8(1): 48-54 (1959)
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