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Zheyu Yan
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2020 – today
- 2024
- [j6]Pietro Melzi
, Ruben Tolosana
FRCSyn-onGoing: Benchmarking and comprehensive evaluation of real and synthetic data to improve face recognition systems. Inf. Fusion 107: 102322 (2024) - [j5]Zheyu Yan
U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1822-1833 (2024) - [j4]Zheyu Yan
Compute-in-Memory-Based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2452-2464 (2024) - [j3]Zhenge Jia
Personalized Meta-Federated Learning for IoT-Enabled Health Monitoring. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3157-3170 (2024) - [c12]Ruiyang Qin, Yuting Hu, Zheyu Yan, Jinjun Xiong, Ahmed Abbasi
FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models : (Invited Paper). ASPDAC 2024: 429-434 - [c11]Yifan Qin, Zheyu Yan, Wujie Wen, Xiaobo Sharon Hu, Yiyu Shi:
Special Session: Sustainable Deployment of Deep Neural Networks on Non-Volatile Compute-in-Memory Accelerators. CODES+ISSS 2024: 37-40 - [c10]Pietro Melzi, Ruben Tolosana, Rubén Vera-Rodríguez, Minchul Kim, Christian Rathgeb, Xiaoming Liu, Ivan DeAndres-Tame, Aythami Morales, Julian Fiérrez, Javier Ortega-Garcia, Weisong Zhao, Xiangyu Zhu, Zheyu Yan, Xiaoyu Zhang, Jinlin Wu, Zhen Lei, Suvidha Tripathi, Mahak Kothari, Md Haider Zama, Debayan Deb, Bernardo Biesseck, Pedro Vidal, Roger Granada, Guilherme P. Fickel, Gustavo Führ, David Menotti, Alexander Unnervik, Anjith George, Christophe Ecabert, Hatef Otroshi-Shahreza, Parsa Rahimi, Sébastien Marcel, Ioannis Sarridis, Christos Koutlis, Georgia Baltsou, Symeon Papadopoulos, Christos Diou, Nicolò Di Domenico, Guido Borghi, Lorenzo Pellegrini, Enrique Mas-Candela, Ángela Sánchez-Pérez, Andrea Atzori
FRCSyn Challenge at WACV 2024: Face Recognition Challenge in the Era of Synthetic Data. WACV (Workshops) 2024: 892-901 - [i21]Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators. CoRR abs/2401.05357 (2024) - [i20]Ruiyang Qin, Yuting Hu, Zheyu Yan, Jinjun Xiong, Ahmed Abbasi, Yiyu Shi:
FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models. CoRR abs/2402.06696 (2024) - [i19]Ruiyang Qin, Zheyu Yan, Dewen Zeng, Zhenge Jia, Dancheng Liu, Jianbo Liu, Zhi Zheng, Ningyuan Cao, Kai Ni, Jinjun Xiong, Yiyu Shi:
Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures. CoRR abs/2405.04700 (2024) - [i18]Ruiyang Qin, Dancheng Liu, Zheyu Yan, Zhaoxuan Tan, Zixuan Pan, Zhenge Jia, Meng Jiang, Ahmed Abbasi, Jinjun Xiong, Yiyu Shi:
Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices. CoRR abs/2406.03777 (2024) - [i17]Yifan Qin, Zheyu Yan, Zixuan Pan, Wujie Wen, Xiaobo Sharon Hu, Yiyu Shi:
TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators. CoRR abs/2406.06544 (2024) - [i16]Zixuan Pan, Jun Xia, Zheyu Yan, Guoyue Xu, Yawen Wu, Zhenge Jia, Jianxu Chen, Yiyu Shi:
Rethinking Medical Anomaly Detection in Brain MRI: An Image Quality Assessment Perspective. CoRR abs/2408.08228 (2024) - [i15]Yifan Qin, Zhenge Jia, Zheyu Yan, Jay Mok, Manto Yung, Yu Liu, Xuejiao Liu, Wujie Wen, Luhong Liang, Kwang-Ting Tim Cheng, X. Sharon Hu, Yiyu Shi:
A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection. CoRR abs/2410.17395 (2024) - 2023
- [c9]Xuan Wang, Zheyu Yan, Chang Meng, Yiyu Shi, Weikang Qian:
DASALS: Differentiable Architecture Search-Driven Approximate Logic Synthesis. ICCAD 2023: 1-9 - [c8]Zheyu Yan, Yifan Qin, Wujie Wen, Xiaobo Sharon Hu, Yiyu Shi:
Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators Through Training with Right-Censored Gaussian Noise. ICCAD 2023: 1-9 - [c7]Zheyu Yan
On the Viability of Using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators. SOCC 2023: 1-6 - [i14]Yifan Qin, Zheyu Yan, Wujie Wen, Xiaobo Sharon Hu, Yiyu Shi:
Negative Feedback Training: A Novel Concept to Improve Robustness of NVCiM DNN Accelerators. CoRR abs/2305.14561 (2023) - [i13]Zheyu Yan, Yifan Qin, Xiaobo Sharon Hu, Yiyu Shi:
On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators. CoRR abs/2306.06923 (2023) - [i12]Zheyu Yan, Yifan Qin, Wujie Wen, Xiaobo Sharon Hu, Yiyu Shi:
Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise. CoRR abs/2307.15853 (2023) - [i11]Pietro Melzi, Ruben Tolosana, Rubén Vera-Rodríguez, Minchul Kim, Christian Rathgeb, Xiaoming Liu, Ivan DeAndres-Tame, Aythami Morales, Julian Fiérrez, Javier Ortega-Garcia, Weisong Zhao, Xiangyu Zhu, Zheyu Yan, Xiaoyu Zhang, Jinlin Wu, Zhen Lei, Suvidha Tripathi, Mahak Kothari, Md Haider Zama
FRCSyn Challenge at WACV 2024: Face Recognition Challenge in the Era of Synthetic Data. CoRR abs/2311.10476 (2023) - [i10]Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections. CoRR abs/2312.06137 (2023) - 2022
- [j2]Tianchen Wang
VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks. IEEE Trans. Computers 71(11): 2717-2727 (2022) - [c6]Zheyu Yan, Weiwen Jiang, Xiaobo Sharon Hu, Yiyu Shi:
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search. ASP-DAC 2022: 128-133 - [c5]Zheyu Yan
SWIM: selective write-verify for computing-in-memory neural accelerators. DAC 2022: 277-282 - [c4]Zheyu Yan
Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous? ICCAD 2022: 87:1-87:9 - [i9]Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators. CoRR abs/2202.08395 (2022) - [i8]Bingqian Lu, Zheyu Yan, Yiyu Shi, Shaolei Ren:
A Semi-Decoupled Approach to Fast and Optimal Hardware-Software Co-Design of Neural Accelerators. CoRR abs/2203.13921 (2022) - [i7]Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
On the Reliability of Computing-in-Memory Accelerators for Deep Neural Networks. CoRR abs/2205.13018 (2022) - [i6]Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous? CoRR abs/2207.07626 (2022) - 2021
- [j1]Weiwen Jiang
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators. IEEE Trans. Computers 70(4): 595-605 (2021) - [c3]Zheyu Yan
Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search. ASP-DAC 2021: 859-864 - [i5]Zheyu Yan, Da-Cheng Juan, Xiaobo Sharon Hu, Yiyu Shi:
Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search. CoRR abs/2107.06871 (2021) - [i4]Zheyu Yan, Weiwen Jiang, Xiaobo Sharon Hu, Yiyu Shi:
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search. CoRR abs/2109.05691 (2021) - 2020
- [c2]Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. ASP-DAC 2020: 163-168 - [c1]Lei Yang, Zheyu Yan
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks. DAC 2020: 1-6 - [i3]Lei Yang, Zheyu Yan, Meng Li, Hyoukjun Kwon, Liangzhen Lai, Tushar Krishna, Vikas Chandra, Weiwen Jiang, Yiyu Shi:
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks. CoRR abs/2002.04116 (2020)
2010 – 2019
- 2019
- [i2]Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo:
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. CoRR abs/1909.04697 (2019) - [i1]Weiwen Jiang, Qiuwen Lou, Zheyu Yan, Lei Yang, Jingtong Hu, Xiaobo Sharon Hu, Yiyu Shi:
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators. CoRR abs/1911.00139 (2019)
Coauthor Index
aka: X. Sharon Hu
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last updated on 2024-12-10 20:50 CET by the dblp team
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