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Shin-Hyun Jeong
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2020 – today
- 2024
- [j4]Shin-Hyun Jeong
, Yong-Un Jeong
An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4628-4632 (2024) - 2022
- [j3]Yong-Un Jeong
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1125-1134 (2022) - 2021
- [j2]Sungphil Choi
A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface. IEEE Access 9: 120285-120296 (2021) - [j1]Yong-Un Jeong
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface. IEEE J. Solid State Circuits 56(4): 1278-1287 (2021) - [c3]Hyunkyu Park, Jihwan Park, Jae-Whan Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim, Joo-Hyung Chae:
A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces. ISCAS 2021: 1-5 - 2020
- [c2]Jaekwang Yun
A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction. A-SSCC 2020: 1-4
2010 – 2019
- 2019
- [c1]Yong-Un Jeong, Joo-Hyung Chae
A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. ISLPED 2019: 1-6
Coauthor Index
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