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Khushboo Rani
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2020 – today
- 2023
- [i2]Khushboo Rani, Hansika Weerasena, Stephen A. Butler, Subodha Charles, Prabhat Mishra:
Modeling and Exploration of Gain Competition Attacks in Optical Network-on-Chip Architectures. CoRR abs/2303.01550 (2023) - [i1]Hansika Weerasena, Zhixin Pan, Khushboo Rani, Prabhat Mishra:
Breaking NoC Anonymity using Flow Correlation Attack. CoRR abs/2309.15687 (2023) - 2022
- [c7]Aruna Jayasena, Khushboo Rani, Prabhat Mishra:
Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks. ICCD 2022: 247-254 - 2021
- [j3]Khushboo Rani, Hemangee K. Kapoor:
Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 633-645 (2021) - 2020
- [c6]Khushboo Rani, Hemangee K. Kapoor:
ZENCO: Zero-bytes based ENCOding for Non-Volatile Buffers in On-Chip Interconnects. DAC 2020: 1-6 - [c5]Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor:
DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects. ISLPED 2020: 151-156
2010 – 2019
- 2019
- [j2]Khushboo Rani, Hemangee K. Kapoor:
Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects. IET Comput. Digit. Tech. 13(6): 481-492 (2019) - [j1]Khushboo Rani, Hemangee K. Kapoor:
Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2191-2204 (2019) - [c4]Khushboo Rani, Hemangee K. Kapoor:
Write Variation Aware Non-volatile Buffers for On-Chip Interconnects. VLSID 2019: 7-12 - 2018
- [c3]Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor:
Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon. ISED 2018: 74-79 - [c2]Ashwini A. Kulkarni, Chirag Joshi, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor:
Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors. ISED 2018: 230-235 - [c1]Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor:
Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors. iSES 2018: 52-57
Coauthor Index
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