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Moritz Schmid
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2010 – 2019
- 2018
- [j5]Christian Schmitt, Moritz Schmid, Sebastian Kuckuk, Harald Köstler
, Jürgen Teich, Frank Hannig
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. Parallel Process. Lett. 28(4): 1850016:1-1850016:21 (2018) - [j4]Oliver Reiche
Loop Parallelization Techniques for FPGA Accelerator Synthesis. J. Signal Process. Syst. 90(1): 3-27 (2018) - 2017
- [j3]Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. J. Signal Process. Syst. 89(2): 225-242 (2017) - 2016
- [p2]Moritz Schmid, Christian Schmitt
Big Data and HPC Acceleration with Vivado HLS. FPGAs for Software Programmers 2016: 115-136 - [p1]Moritz Schmid, Oliver Reiche
HIPAcc. FPGAs for Software Programmers 2016: 205-223 - 2015
- [b1]Moritz Schmid:
Rapid Prototyping for Hardware Accelerators in the Medical Imaging Domain. University of Erlangen-Nuremberg, 2015 - [j2]Oliver Reiche
Synthesis and optimization of image processing accelerators using domain knowledge. J. Syst. Archit. 61(10): 646-658 (2015) - [c12]Moritz Schmid, Oliver Reiche
Loop coarsening in C-based High-Level Synthesis. ASAP 2015: 166-173 - 2014
- [c11]Moritz Schmid, Alexandru Tanase, Frank Hannig
Domain-specific augmentations for High-Level Synthesis. ASAP 2014: 173-177 - [c10]Oliver Reiche
Code generation from a domain-specific language for C-based HLS of hardware accelerators. CODES+ISSS 2014: 17:1-17:10 - [c9]Moritz Schmid, Nicolas Apelt, Frank Hannig
An image processing library for C-based high-level synthesis. FPL 2014: 1-4 - [i1]Moritz Schmid, Oliver Reiche, Christian Schmitt, Frank Hannig, Jürgen Teich:
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs. CoRR abs/1408.4721 (2014) - 2013
- [c8]Frank Hannig
System integration of tightly-coupled processor arrays using reconfigurable buffer structures. Conf. Computing Frontiers 2013: 2:1-2:4 - [c7]Moritz Schmid, Frank Hannig
High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model. PARCO 2013: 497-506 - [c6]Moritz Schmid, Markus Blocherer, Frank Hannig
Real-timerange image preprocessing on FPGAs. ReConFig 2013: 1-8 - 2012
- [j1]Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig
Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Design Autom. Electr. Syst. 18(1): 2:1-2:25 (2012) - [c5]Moritz Schmid, Frank Hannig
Power Management Strategies for Serial RapidIO Endpoints in FPGAs. FCCM 2012: 101-108 - 2011
- [c4]Jakob Wasza, Sebastian Bauer, Sven Haase, Moritz Schmid, Sebastian Reichert, Joachim Hornegger:
RITK: The Range Imaging Toolkit - A Framework for 3-D Range Image Stream Processing. VMV 2011: 57-64 - 2010
- [c3]Hritam Dutta, Frank Hannig
Modeling and synthesis of communication subsystems for loop accelerator pipelines. ASAP 2010: 125-132 - [c2]Frank Hannig
A deeply pipelined and parallel architecture for denoising medical images. FPT 2010: 485-490
2000 – 2009
- 2008
- [c1]Moritz Schmid, Daniel Ziener
Netlist-level IP protection by watermarking for LUT-based FPGAs. FPT 2008: 209-216
Coauthor Index
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